CY8CMBR2110-24LQXI Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY8CMBR2110-24LQXI Datasheet PDF : 71 Pages
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Schematic 2: Eight Buttons with Analog Voltage Output
Figure 2. CY8CMBR2110 Schematic 2
CY8CMBR2110
In Figure 2, the device is configured in the following manner:
■ CS0–CS7 pins: 560 to CapSense buttons; CS8, CS9 pins:
Ground
❐ Eight CapSense buttons (CS0–CS9)
❐ CS8 and CS9 buttons not used in design
■ GPO0–GPO7: To external resistive network
❐ Eight GPOs (GPO0–GPO7) used for Analog Voltage Output
❐ GPO8 and GPO9 not used in design
■ CMOD pin: 2.2 nF to ground
❐ Modulating capacitor
■ XRES pin: Floating
❐ For external reset
■ BuzzerOut0 and BuzzerOut1 pins: To AC buzzer
❐ AC Buzzer (2-pin)
■ HostControlGPO0, HostControlGPO1 pins: LED and 5 kto
ground
❐ Two Host-controlled GPOs
■ I2C_SDA, I2C_SCL pins: 330-to I2C header
❐ For I2C communication
■ Attention/Sleep pin: To Host
❐ For controlling I2C communication, power consumption, and
device operating mode
Document Number: 001-74494 Rev. *B
Page 5 of 71
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