CY7C1471V33-133AXC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1471V33-133AXC
Cypress Semiconductor
CY7C1471V33-133AXC Datasheet PDF : 32 Pages
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CY7C1471V33
CY7C1473V33
CY7C1475V33
Pin Definitions
Name
IO
Description
A0, A1, A
BWA, BWB,
BWC, BWD,
BWE, BWF,
BWG, BWH
WE
ADV/LD
CLK
CE1
CE2
CE3
OE
CEN
ZZ
Input-
Synchronous
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK. A[1:0] are fed to the two-bit burst counter.
Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK.
Input-
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
Synchronous This signal must be asserted LOW to initiate a write sequence.
Input-
Synchronous
Advance/Load Input. Advances the on-chip address counter or loads a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When
LOW, a new address can be loaded into the device for an access. After being deselected,
ADV/LD should must driven LOW to load a new address.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select or deselect the device.
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select or deselect the device.
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select or deselect the device.
Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic
block inside the device to control the direction of the IO pins. When LOW, the IO pins are
enabled to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as
input data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state, when the device is deselected.
Input-
Clock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by
Synchronous the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN
does not deselect the device, use CEN to extend the previous cycle when required.
Input-
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
Asynchronous condition with data integrity preserved. During normal operation, this pin must be LOW or
left floating. ZZ pin has an internal pull down.
DQs
DQPX
MODE
VDD
VDDQ
VSS
IO-
Synchronous
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The
outputs are automatically tri-stated during the data portion of a write sequence, during the
first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
IO-
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During
Synchronous write sequences, DQPX is controlled by BWX correspondingly.
Input Strap Pin Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects
interleaved burst sequence.
Power Supply Power supply inputs to the core of the device.
IO Power Supply Power supply for the IO circuitry.
Ground
Ground for the device.
Document #: 38-05288 Rev. *J
Page 8 of 32
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