PE42553 Ver la hoja de datos (PDF) - Peregrine Semiconductor Corp.
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PE42553 Datasheet PDF : 19 Pages
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PE42553
UltraCMOS® SPDT RF Switch
Peregrine’s HaRP technology enhancements deliver high linearity and excellent harmonics performance. It is an
innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and
integration of conventional CMOS.
Optional External VSS Control
For proper operation, the VSS_EXT control pin must be grounded or tied to the VSS voltage specified in Table 2.
When the VSS_EXT control pin is grounded, FETs in the switch are biased with an internal negative voltage
generator. For applications that require the lowest possible spur performance, VSS_EXT can be applied externally
to bypass the internal negative voltage generator.
Absolute Maximum Ratings
Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be
restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for
extended periods may reduce reliability.
ESD Precautions
When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices.
Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to
avoid exceeding the rating specified in Table 1.
Latch-up Immunity
Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up.
Table 1 • Absolute Maximum Ratings for PE42553
Parameter/Condition
Supply voltage, VDD
Digital input voltage, CTRL
LS input voltage
RF input power, CW (RFC–RFX)(1)
9 kHz–10 MHz
>10 MHz–8 GHz
RF input power, pulsed (RFC–RFX)(2)
9 kHz–10 MHz
>10 MHz–8 GHz
RF input power into terminated ports, CW (RFX)(1)
9–800 kHz
>800 kHz–8 GHz
Storage temperature range
ESD voltage HBM(3)
RF pins to GND
All pins
Min
–0.3
–0.3
–0.3
–65
Max
5.5
3.6
3.6
Unit
V
V
V
Fig. 2, Fig. 3
37
dBm
dBm
Fig. 2, Fig. 3
Fig. 4, Fig. 5
dBm
dBm
Fig. 2, Fig. 3
28
+150
dBm
dBm
°C
4000
V
2500
V
Page 2
www.psemi.com
DOC-62463-2 – (11/2014)
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