LC72133V Ver la hoja de datos (PDF) - SANYO -> Panasonic

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LC72133V

PLL Frequency Synthesizer for Electronic Tuning

SANYO -> Panasonic 

LC72133M, 72133V

Continued from preceding page.

No.

Control block/data

IF counter control data

(11) IFS

LSI test data

TEST 0 to TEST 2

(12)

(13) DNC

Functions

• Note that if this value is set to zero the system enters input sensitivity degradation mode,

and the sensitivity is reduced to 10 to 30 mV rms.

* See the “IF Counter Operation” item for details.

• LSI test data

TEST0

TEST1 These values must all be set to 0.

TEST2

These test data are set to 0 automatically after the power-on reset.

Don’t care. This data must be set to 0.

3. DO Output Data (Serial Data Output)

• OUT Mode

Related data

4. DO Output Data

No.

Control block/data

I/O port data

I2, I1

(1)

PLL unlock data

(2) UL

IF counter binary data

(3) C19 to C0

Functions

• Latched from the pin states of the IO1 and IO2 I/O ports.

• These values follow the pin states regardless of the input or output setting.

• Data is latched at the point where the circuit enters data output mode (OUT mode).

I1 ← IO1 pin state High: 1

I2 ← IO2 pin state Low: 0

• Latched from the state of the unlock detection circuit.

UL ← 0: Unlocked

UL ← 1: Locked or detection stopped mode

• Latched from the value of the IF counter (20-bit binary counter).

C19 ← MSB of the binary counter

C0 ← LSB of the binary counter

Related data

IOC1,

IOC2

UL0,

UL1

CTE,

GT0,

GT1

No. 5427-11/22

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