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CS8900

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CONTENTS

1.0 INTRODUCTION

1.1 General Description . . . . 4

1.2 System Applications . . . . 4

1.3 Key Features and Benefits . . . 6

1.4 Typical Connection Diagram . . 7

2.0 PIN DESCRIPTION

2.1 Pin Diagram . . . . . . 8

2.2 Pin Description . . . . . . 9

3.0 FUNCTIONAL DESCRIPTION

3.1 Overview . . . . . . . 13

3.2 ISA Bus Interface . . . . . 14

3.3 Reset and Initialization . . . . 15

3.1 Configuration with EEPROM . . 13

3.5 Programming the EEPROM . . 20

3.6 Boot PROM Operation . . . . 22

3.7 Low-Power Modes . . . . . 22

3.8 LED Outputs . . . . . . 24

3.9 Media Access Control (MAC) . . 25

3.10 Encoder/Decoder (ENDEC) . . 30

3.11 10BASE-T Transceiver . . . . 31

3.12 Attachment Unit Interface (AUI) . 34

35 External Clock Oscillator . . . 35

4.0 PACKETPAGE ARCHITECTURE

4.1 PacketPage Overview . . . . 36

4.2 PacketPage Memory Map . . . 37

4.3 Bus Interface Registers

Product Identification Code . . 38

I/O Base Address . . . . . 38

Interrupt Number . . . . . 39

DMA Channel Number . . . 39

DMA Start of Frame . . . . 40

DMA Frame Count . . . . 40

RxDMA Byte Count . . . . 41

Memory Base Address . . . 41

Boot PROM Base Address . . 42

Boot PROM Address Mask . . 42

EEPROM Command . . . . 43

EEPROM Data . . . . . 43

Receive Frame Byte Counter . . 43

CS8900

4.4 Status and Event Registers . . . 44

4.4.1 Status/Control Bit Definitions 45

4.4.2 Status/Control Register Summary 46

4.4.3 Status/Control Register Details

(0) Interrupt Status Queue . . . 48

(3) Receiver Configuration (RxCFG) 49

(4) Receiver Event (RxEvent) . . 50

(5) Receiver Control (RxCTL) . 51

(7) Transmit Configuration (TxCFG) 52

(8) Transmit Event (TxEvent) . . 53

(9) Transmit Command (TxCMD) 54

(B) Buffer Configuration (BufCFG) 55

(C) Buffer Event (BufEvent) . . 57

(10) Receive Miss Counter (RxMISS) 58

(12) Trans. Collision Count (TxCOL) 59

(13) Line Control (LineCTL) . . 60

(14) Line Status (LineST) . . . 61

(15) Self Control (SelfCTL) . . 62

(16) Self Status (SelfST) . . . 63

(17) Bus Control (BusCTL) . . 64

(18) Bus Status (BusST) . . . 65

(19) Test Control (TestCTL) . . 66

(1C) AUI Time Domain Reflectometer 67

4.5 Initiate Transmit Registers

Transmit Command (TxCMD) . 68

Transmit Length (TxLength) . . 69

4.6 Address Filter Registers

Logical Address Table (hash table) 70

Individual Address (IEEE address) 70

4.7 Receive and Transmit Frame Locations 71

4.8 8 and 16-bit Transfers . . . . 71

4.9 Memory Mode Operation . . . 72

4.10 I/O Space Operation . . . . 74

5.0 OPERATION

5.1 Managing Interrupts and

Servicing the Interrupt Status Queue 77

5.2 Basic Receive Operation . . . 79

5.3 Receive Frame Address Filtering . 86

5.4 Receive DMA . . . . . . 89

5.5 Auto-Switch DMA . . . . . 94

5.6 StreamTransfer . . . . . . 97

99 Transmit Operation . . . . . 99

5.8 Full Duplex Operation . . . . 106

5.9 Auto-Negotiation Considerations . 106

2

DS150PP2

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