DS2175S Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

Lista de partido

DS2175S

T1/CEPT Elastic Store

Maxim Integrated 

RECEIVE SIDE TIMING (RCLK = 1.544 MHz) Figure 2

DS2175

RECEIVE SIDE TIMING (RCLK = 2.048 MHz) Figure 3

NOTES:

1. All channel data is passed through the elastic store in 2.048 MHz system side applications

(SCLKSEL = 1);

2. Data in channels >24 is ignored in 1.544 MHz system side applications (SCLKSEL = 0).

SYSTEM MULTIFRAME BOUNDARY TIMING (SYSCLK = 1.544 MHz) Figure 4

NOTES:

1. In 1.544 MHz receive side applications (RCLKSEL=0), the F–bit position contains F–bit data

extracted from the data stream at RSER. The F–bit position is forced to “1” in 2.048 MHz receive

side applications (RCLKSEL=1).

2. In 2.048 MHz receive side applications (RCLKSEL=1), the E–bit position is forced to “1” and data in

channels >24 is ignored.

5 of 12

Share Link: