ICS9248F-72 Ver la hoja de datos (PDF) - Integrated Circuit Systems
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ICS9248F-72 Datasheet PDF : 12 Pages
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ICS9248-72
Preliminary Product Preview
Byte 1: CPU, CPU/2, 48MHz Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
27
28
-
42
-
39
36
35
PWD
1
1
-
1
-
1
1
1
Description
48MHz
24_48 MHz
(Reserved)
CPU/2
(Reserved)
CPUCLK 2
CPUCLK 1
CPUCLK 0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 2: PCICLK Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
16
15
13
12
11
10
8
7
PWD
1
1
1
1
1
1
1
1
Description
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: 3V66, REF Register Active/Inactive
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
23
22
21
-
-
19
18
PWD
0
1
1
1
X
X
1
1
Description
(Reserved)
3V66_2
3V66_1
3V66_0
FS2#
(SEL24 48#)#
PCICLK9
PCICLK8
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 4: IOAPIC, REFRegisterActive/Inactive
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
1
45
46
-
-
-
2
PWD
0
1
1
1
0
X
X
1
Description
(Reserved)
IOAPIC2
IOAPIC1
IOAPIC0
(Reserved)
FS0#
FS1#
REF (X2)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 5: CPU, IOAPIC RegisterActive/Inactive
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
-
-
-
-
PWD
0
0
0
0
0
0
0
0
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
6
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