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79R4640-100DU

Low-Cost Embedded 64-bit RISController w/ DSP Capability

Integrated Device Technology 

IDT79RC4640™

address is “in bounds”, the value of the corresponding “base” register is

added to the virtual address to form the physical address for that refer-

ence. If the address is not within bounds, an exception is signalled.

This facility enables multiple user processes in a single physical

memory without the use of a TLB. This type of operation is further

supported by a number of development tools for the RC4640, including

real-time operating systems and “position independent code”.

Kernel mode addresses do not use the base-bounds registers, but

rather undergo a fixed virtual-to-physical address translation.

Debug Support

To facilitate software debug, the RC4640 adds a pair of “watch” regis-

ters to CP0. When enabled, these registers will cause the CPU to take

an exception when a “watched” address is appropriately accessed.

Interrupt Vector

The RC4640 also adds the capability to speed interrupt exception

decoding. Unlike the RC4700, which utilizes a single common exception

vector for all exception types (including interrupts), the RC4640 allows

kernel software to enable a separate interrupt exception vector. When

enabled, this vector location speeds interrupt processing by allowing

software to avoid decoding interrupts from general purpose exceptions.

Cache Memory

To keep the RC4640’s high-performance pipeline full and operating

efficiently, the RC4640 incorporates on-chip instruction and data caches

that can each be accessed in a single processor cycle. Each cache has

its own 64-bit data path and can be accessed in parallel. The cache

subsystem provides the integer and floating-point units with an aggre-

gate bandwidth of over 3200 MB per second at a pipeline clock

frequency of 267MHz. The cache subsystem is similar in construction to

that found in the RC4700, although some changes have been imple-

mented. Table 4 is an overview of the caches found on the RC4640.

Instruction Cache

The RC4640 incorporates a two-way set associative on-chip instruc-

tion cache. This virtually indexed, physically tagged cache is 8KB in size

and is parity protected.

Because the cache is virtually indexed, the virtual-to-physical

address translation occurs in parallel with the cache access, thus further

increasing performance by allowing these two operations to occur simul-

taneously. The tag holds a 20-bit physical address and valid bit, and is

parity protected.

The instruction cache is 64-bits wide, and can be refilled or accessed

in a single processor cycle. Instruction fetches require only 32 bits per

cycle, for a peak instruction bandwidth of 1068MB/sec at 267MHz.

Sequential accesses take advantage of the 64-bit fetch to reduce power

dissipation, and cache miss refill, can write 64 bits-per-cycle to minimize

the cache miss penalty. The line size is eight instructions (32 bytes) to

maximize performance.

In addition, the contents of one set of the instruction cache (set “A”)

can be “locked” by setting a bit in a CP0 register. Locking the set

prevents its contents from being overwritten by a subsequent cache

miss; refill occurs then only into “set B”.

This operation effectively “locks” time critical code into one 4kB set,

while allowing the other set to service other instruction streams in a

normal fashion. Thus, the benefits of cached performance are achieved,

while deterministic real-time response is preserved.

Data Cache

For fast, single cycle data access, the RC4640 includes an 8KB on-

chip data cache that is two-way set associative with a fixed 32-byte

(eight words) line size. Table 4 lists the RC4640 cache attributes.

Characteristics

Instruction

Data

Size

Organization

Line size

8KB

8KB

2-way set associative 2-way set associative

32B

32B

Index

Tag

Write policy

Line transfer order

vAddr11..0

pAddr31..12

n.a.

vAddr11..0

pAddr31..12

writeback /writethru

read sub-block order read sub-block order

write sequential

Miss restart after transfer of entire line

write sequential

first word

Parity

Cache locking

per-word

set A

per-byte

set A

Table 4 RC4640 Cache Attributes

The data cache is protected with byte parity and its tag is protected

with a single parity bit. It is virtually indexed and physically tagged to

allow simultaneous address translation and data cache access

The normal write policy is writeback, which means that a store to a

cache line does not immediately cause memory to be updated. This

increases system performance by reducing bus traffic and eliminating

the bottleneck of waiting for each store operation to finish before issuing

a subsequent memory operation. Software can however select write-

through for certain address ranges, using the CAlg register in CP0.

Cache protocols supported for the data cache are:

◆ Uncached.

Addresses in a memory area indicated as uncached will not be

read from the cache. Stores to such addresses will be written

directly to main memory, without changing cache contents.

◆ Writeback.

Loads and instruction fetches will first search the cache, reading

main memory only if the desired data is not cache resident. On

data store operations, the cache is first searched to see if the

target address is cache resident. If it is resident, the cache con-

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December 5, 2008

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