IDT72265LA15PFG Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT72265LA15PFG

CMOS SuperSync FIFO™ 8,192 x 18 16,384 x 18

Integrated Device Technology 

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT

Mode), for the relevant timing diagram.

For either IDT Standard mode or FWFT mode, updating of the PAE,

HF and PAF flags begin with the rising edge of RCLK that RT is setup.

PAE is synchronized to RCLK, thus on the second rising edge of RCLK

after RT is setup, the PAE flag will be updated. HF is asynchronous, thus

the rising edge of RCLK that RT is setup will update HF. PAF is synchro-

nized to WCLK, thus the second rising edge of WCLK that occurs tSKEW

after the rising edge of RCLK that RT is setup will update PAF. RT is

synchronized to RCLK.

11

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