5962-9317708QTC Ver la hoja de datos (PDF) - Atmel Corporation

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5962-9317708QTC

Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO

Atmel Corporation 

Pin Description

Data In (I0 - I8)

Reset (RS)

M67206H

Names

I0-8

Q0-8

W

R

RS

EF

FF

XO/HF

XI

FL/RT

VCC

GND

Description

Inputs

Outputs

Write Enable

Read Enable

Reset

Empty Flag

Full Flag

Expansion Out/Half-Full Flag

Expansion IN

First Load/Retransmit

Power Supply

Ground

Data inputs for 9-bit data

Reset occurs whenever the Reset (RS) input is taken to a low state. Reset returns both

internal read and write pointers to the first location. A reset is required after power-up

before a write operation can be enabled. Both the Read Enable (R) and Write Enable

(W) inputs must be in the high state during the period shown in Figure 1 (i.e. tRSS before

the rising edge of RS) and should not change until tRSR after the rising edge of RS. The

Half-Full Flag (HF) will be reset to high After Reset (RS)

Figure 1. Reset

4143J–AERO–04/07

Notes: 1. EF, FF and HF may change status during reset, but flags will be valid at tRSC.

2. W and R = VIH around the rising edge of RS.

3

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