BR24G1MNUX-3AE2(2013) Ver la hoja de datos (PDF) - ROHM Semiconductor
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BR24G1MNUX-3AE2
(Rev.:2013)
(Rev.:2013)
ROHM Semiconductor
BR24G1MNUX-3AE2 Datasheet PDF : 38 Pages
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BR24Gxxx-3A (128K 256K 1M)
Datasheet
Write Command
1. Write Cycle
(1) Arbitrary data can be written to EEPROM. When writing only 1 byte, Byte Write is normally used, and when
writing continuous data of 2 bytes or more, simultaneous write is possible by Page Write cycle. The maximum
number of write bytes is specified per device of each capacity.
Up to 256 arbitrary bytes can be written.（In the case of BR24G1M-3A）
SDA
LINE
S
W
T
R
A
I
R
SLAVE T
1st WORD
T
ADDRESS E
ADDRESS
1 0 1 0 A2 A1 A0
WAWA
15 14
RA
A
Note)
/C
(1)
C
WK
K
Figure 38. Byte Write Cycle
2nd WORD
ADDRESS
WA D7
0
A
C
K
DATA
S
T
O
P
(1) As for WA14, BR24G128-3A becomes don't care.
As for WA15, BR24G128/256-3A becomes don't care.
D0
A
C
K
SDA
LINE
S
W
T
R
A
I
R
SLAVE
T
T
ADDRESS
E
1st WORD
ADDRESS(n)
1 0 1 0 A2 A1 A0
WA WA
15 14
00
Note )
RA
/C
(1)
WK
2nd WORD
ADDRESS(n)
DATA(n)
WA
D7
D0
0
A
A
A
C
C
C
K
K
K
Figure 39 Page Write Cycle
S
T
(2)
O
DATA(n+63)
P
D0
A
C
K
(1) As for WA14, BR24G128-3A becomes don't care.
As for WA15, BR24G128/256-3A becomes don't care.
(2) As for BR24G128/256-3A becomes (n+63)
As for BR24G1M-3A becomes (n+255)
Note)
(1)
1 0 1 0 A 2A 1A 0
(1) In BR24G1M-3A A0 becomes P0.
Figure 40. Difference of Slave Address of Each Type
(2) During internal write execution, all input commands are ignored, therefore ACK is not returned.
(3) Data is written to the address designated by word address (n-th address)
(4) By issuing stop bit after 8bit data input, internal write to memory cell starts.
(5) When internal write is started, command is not accepted for tWR (5ms at maximum).
(6) Using page write cycle, writing in bulk is done as follows: Up to 64Byte (BR24G128-3A, BR24G256-3A）
Up to 256Byte (BR24G1M-3A）
The bytes in excess overwrite the data already sent first.
(Refer to "Internal Address Increment")
(7) As for page write cycle of BR24G128-3A and BR24G256-3A, where 2 or more bytes of data is intended to be
written, after the 8 significant bits (BR24G128-3A) or 9 significant bits (BR24G256-3A) of word address are
designated arbitrarily, only the value of 6 least significant bits in the address is incremented internally, so that data
up to 64 bytes of memory only can be written.
(8) As for page write cycle of BR24G1M-3A, where 2 or more bytes of data is intended to be written, after the page
select bit ‘P0’ of slave, and the 8 significant bits of word address are designated arbitrarily, only the value of 8
least significant bits in the address is incremented internally, so that data up to 256 bytes of memory only can be
written
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25.Feb.2013 Rev.002
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