L9904(2002) Ver la hoja de datos (PDF) - STMicroelectronics

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L9904
(Rev.:2002)

MOTOR BRIDGE CONTROLLER

STMicroelectronics 

L9904

FUNCTIONAL DESCRIPTION (continued)

Programmable cross conduction protection

The external power MOS transistors in H-Bridge ( two half bridges) configuration are switched on with an addi-

tional delay time tCCP to prevent cross conduction in the halfbridge. The cross conduction protection time

tCCP is determined by the external capacitor CPR and resistor RPR at the PR pin. The capacitor CPR is charged

up to the voltage limit VPRH. A level change on the control inputs DIR and PWM switches off the concerned ex-

ternal MOS transistor and the charging source at the PR pin. The resistor RPR discharges the capacitor CPR.

The concerned external power MOS transistor will be switched on again when the voltage at PR reaches the

value of VPRL. After that the CPR will be charged again. The capacitor CPR should be choosen between 100pF

and 1nF. The resistor RPR should be higher than 7kW. The delay time can be expressed as follows:

tCCP= RPR · CPR · ln NPR

with NPR= VPRH / VPRL = 2

tCCP= 0.69 · RPR · CPR

ISO-Interface

The ISO-Interface provides the communication between the micro controller and a serial bus with a baud rate

up to 60kbit/s via a single wire which is VBAT and GND compatible. The logic level transmission input TX drives

the open drain K-output. The K output can be connected to a serial bus with a pull up resistor to VBAT. The K-

pin is protected against overvoltage, short to GND and VS and can be driven beyond VVS and GND. During lack

of VVS or GND the output shows high impedance characteristic. The open drain output RX with an internal pull

up resistor monitors the status at the K-pin to read the received data and control the transmitted data. Short

circuit condition at K-pin is recognized if the internal open drain transistor isn't able to pull the voltage potential

at K-pin below the threshold of 0.45·VVS. Then the RX stays in high condition. A timer starts and switches the

open drain transistor after typ. 20µs off. A next low at the TX input resets the timer and the open drain transistor

switches on again.

Figure 8. Functional schematic of the ISO-interface

RX

R RX

VCC

K

= 0.5 •V VS

R TX

TX

I KH

R

Q

S

R delay

TSH

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