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MC44354DW Datasheet PDF : 20 Pages
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MC44353 MC44354 MC44355
The device has two main sections; a PLL section to
synthesize the channel frequency of the UHF output and a
modulator section which accepts audio and video inputs and
modulates the UHF carrier with them.
The channel frequency, sound and picture modulation
index and sound/picture carrier ratio are all programmable by
means of a high speed I2C compatible bus. An on–chip video
test pattern generator with an audio test signal is also
The MC44353 is designed to operate as a multi–standard
modulator and can handle the systems B/G, D/K, H, I, L and
N with the same external circuit components. The basic
elements of the circuit are shown in Figure 1.
comparator output pin. The tuning voltage range is then from
just above 0 V to VCC (5.0 V typical) and therefore not all
channels can be synthesised without adjusting the circuit
Control bits T0, T1 and T2 are used to control the
operational state of the phase comparator. A truth table is
shown in the control bits section.
Figure 13. Output Configuration of
the Phase Comparator
The Bus Receiver
The bus receiver operates I2C compatible bus data
format. Additional information on the data format is given on
page 5. The chip address (I2C bus) is: 1 1 0 0 1 0 1 0 (ACK)
= $CA (hex). Each ninth data bit (bits 9, 18, 27, 36 and 45) is
an ACK (acknowledge bit) during which the MCU sends a
logic “1” and the Modulator circuit answers on the data line by
pulling low. Besides the chip address the circuit needs 4 data
bytes for operation. These bytes are defined in the section on
control bits. The following sequences of data bytes are
Example 1 CA C1 C0
Example 2 CA FM FL
Example 3 CA C1 C0 FM FL
Example 4 CA FM FL C1 C0
For the significance of the control bits the section on
control and test bit assignments on pages 11 and 12 should
be consulted.
4.0 µA
4.0 µA
Amp In
30 V
STATE 4: Normal operation with
inverted charge polarity.
Amp In
560 k
240 k
Op Out
The programmable divider
The programmable divider’s division ratio is controlled by
the state of control bits N0 to N11. The division ratio is given
N = 2048*N11+ 1024*N10 + . . . . + 4*N2 + 2*N1 + N0.
Max. ratio = 4095
Min. ratio = 17.
10 nF
4.7 nF
330 pF
STATE 0: Normal operations with non–inverted
charge polarity.
Amp In
The prescaler
The prescaler is a fixed divide by 8 and is permanently
engaged. It has a pre–amplifier for high sensitivity and good
decoupling from the RF section.
4.7 nF
10 nF
240 k
The phase comparator
The phase comparator has a current source/sink
characteristic (charge pump, see Figure 13). The pump
current is 4.0 µA. In normal operation (State 4) the phase
comparator pulls high if the UHF oscillator frequency is too
high. An internal amplifier is provided to generate tuning
voltages greater than 5.0 V while inverting the output.
The phase comparator can also be programmed to work
(in state 0) with the opposite charge pump polarity. In this
case the phase comparator pulls low if the UHF frequency is
too high. In this mode the amplifier is not required. The filter
components may be connected directly to the phase
The reference divider
This divider divides by 128 resulting in a reference
frequency of 31.25 kHz with a 4.0 MHz crystal. The UHF
oscillator frequency may be synthesised in steps of 250 kHz.
The 250 kHz steps are due to the presence of a divide by 8
prescaler prior to the programmable divider. The reference
divider also generates the timing signals TE1 and TE2 for the
on-chip test pattern generator and the audio test signal. The
reference divider also provides the 7.8 kHz reference
frequency for the Sound PLL.

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