CS493263-DL Ver la hoja de datos (PDF) - Cirrus Logic
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CS493263-DL Datasheet PDF : 90 Pages
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CS49300 Family DSP
1.8. Switching Characteristics — Intel® Host Mode
(VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)
Parameter
Symbol
Min
Address setup before CS and RD low or CS and WR low
Tias
5
Address hold time after CS and RD low or CS and WR low
Tiah
5
Delay between RD then CS low or CS then RD low
Ticdr
0
Data valid after CS and RD low
(Note 3)
Tidd
-
CS and RD low for read
(Note 1)
Tirpw
DCLKP + 10
Data hold time after CS or RD high
Tidhr
5
Data high-Z after CS or RD high
(Note 2)
Tidis
-
CS or RD high to CS and RD low for next read
(Note 1)
Tird
2*DCLKP + 10
CS or RD high to CS and WR low for next write (Note 1) Tirdtw 2*DCLKP + 10
Delay between WR then CS low or CS then WR low
Ticdw
0
Data setup before CS or WR high
Tidsu
20
CS and WR low for write
(Note 1) Tiwpw
DCLKP + 10
Data hold after CS or WR high
Tidhw
5
CS or WR high to CS and RD low for next read (Note 1) Tiwtrd 2*DCLKP + 10
CS or WR high to CS and WR low for next write (Note 1) Tiwd 2*DCLKP + 10
Max
-
-
∞
21
-
-
22
-
-
∞
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLKP, in nanoseconds. DCLKP =
1/DCLK. The DSP clock can be defined as follows:
External CLKIN Mode:
DCLK == CLKIN/4 before and during boot
DCLK == CLKIN after boot
Internal Clock Mode:
DCLK == 10MHz before and during boot, i.e. DCLKP == 100ns
DCLK == 65 MHz after boot, i.e. DCLKP == 15.4ns
It should be noted that DCLK for the internal clock mode is application specific. The application code
users guide should be checked to confirm DCLK for the particular application.
2. This specification is characterized but not production tested. A 470 ohm pull-up resistor was used for
characterization to minimize the effects of external bus capacitance.
3. See Tidd from Intel Host Mode in Table 6 on page 46
10
DS339F7
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