HSP9520 Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
Lista de partido
HSP9520 Datasheet PDF : 4 Pages
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Block Diagram
I0
D0 - D7
8
CLK
I1
HSP9520, HSP9521
REG. A1
REG. A2
REG. B1
REG. B2
MUX
8
Y0 - Y7
OE
S0
S1
Pin Descriptions
NAME DIP PIN TYPE
DESCRIPTION
VCC
24
GND
12
The +5V Power Supply Pin. A 0.1µF capacitor between the VCC and GND pin is recommended.
The device ground.
CLK
11
I
Input Clock. Data is latched on the low to high transition of this clock signal. Input setup and hold times with
respect to the clock must be met for proper operation.
D0-7
3-10
I
Data Input Port. These inputs are used to supply the 8 bits of data which will be latched into the selected
register on the next rising clock edge.
Y0-7
21-14
O Data Output Port. This 8-bit port provides the output data from the four internal registers. They are provided in
a multiplexed fashion, and are controlled via the multiplexer control inputs (S0 and S1).
I0, I1
1, 2
I
Instruction Control Inputs. These inputs are used to provide the instruction code which determines the internal
register pipeline configuration. Refer to the Instruction Control Table for the specific codes and their associated
configurations.
S0, S1
23, 22
I
Multiplexer Control Inputs. These inputs select which of the four internal registers contents will be available at
the output port. Refer to the Register Select Table for the codes to select each register.
OE
13
I
Output Enable. This input controls the state of the output port (Y0 - Y7). A LOW on this control line enables
the port for output. When OE is HIGH, the output drivers are in the high impedance state. Internal latching or
transfer of data is not affected by this pin.
2
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