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STLC1511 Datasheet PDF : 31 Pages
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STLC1511
During a transaction, the first bit sent to the AFE de-
termines the type of transaction, R/W=”1” corre-
sponds to a read transaction while R/W=”0”
corresponds to a write transaction. The next three
bits, address[a2:a0], determine which of the 8 AFE
registers will be accessed (Table 8). This is followed
by the 8-bit data word.
In both Read and Write transactions, bit 0 (LSB) of
the serially transferred 8-bit word is clocked from the
data source first (the data source being the external
DSP during Write transactions; the STLC1511 during
Read transactions).
The definition of these fields within the 8-bit word is
outlined below in Table 8 and in the detailed register
maps following.
When the voltage on the RESETN pin is low, the bits
in the control register will be reset as per defined in
the detailed register maps.
For a write operation, the data on the DRX pin is
latched into the STLC1511 on the negative edge of
the DIGCLK signal. The data should change state on
the positive edge of the clock.
For a read operation, the data on the DTX pin is out-
put on the positive edge of the clock on pin DIGCLK.
Table 8. AFE Register Map Summary
Addr
[a2:a0]
Name
D7
D6
D5
D4
D3
D2
D1
D0 Type
000
STLC1511 Control 1 (Rx Rx PGA Gain
RW
PGA Gain)
001
STLC1511 Control 2 (Tx not used
Tx PGA Gain
RW
PGA Gain)
010
STLC1511 Control 3
(Power Down Reg)
not used
Rx
not
Opa use
mp d
Pow
er
Dow
n
Rx
Tx
RW
Pow Pow
er
er
Dow Dow
n
n
011
STLC1511 Control 4
not
(Misc. Control)
use
d
DIV Output
(Test mode)
PLL Tx
Clip RW
PFD Loo Indic
inpu p
ator
t sel back ena
ble
100
AFE Control 5
(PLL Control)
not DIG- FREF Mode PLL Osc Clock Source R/W
use REF
Mod Mod Control
d
Ena
ble
e
e1
101
not used
not used
110
not used
not used
111
AFE Status
not used
Clip R
Stat
us
<1>Presently there is no difference in the oscillator driver between Oscillator Mode and CPE modes so this bit is unused. However,
it may be required in the future and should be programmed correctly in case needed.
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