MC54HC533A Ver la hoja de datos (PDF) - Motorola => Freescale
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MC54HC533A Datasheet PDF : 7 Pages
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MC54/74HC533A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol
Parameter
Guaranteed Limit
VCC – 55 to 25_C
v 85_C
v 125_C
Fig. Volts Min Max Min Max Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu Minimum Setup Time, Input D to Latch Enable
4
2.0 25
30
40
ns
3.0 20
25
30
4.5 5.0
6.0
8.0
6.0 5.0
6.0
7.0
th
Minimum Hold Time, Latch Enable to Input D
4
2.0 5.0
5.0
5.0
ns
3.0 5.0
5.0
5.0
4.5 5.0
5.0
5.0
6.0 5.0
5.0
5.0
tw Minimum Pulse Width, Latch Enable
2
2.0 60
75
90
ns
3.0 23
27
32
4.5 12
15
18
6.0 10
13
15
tr, tf Maximum Input Rise and Fall Times
1
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000 ns
800
500
400
SWITCHING WAVEFORMS
INPUT D
tr
90%
50%
10%
tPHL
90%
Q
50%
10%
tTHL
Figure 1.
OUTPUT
ENABLE
50%
tPZL
tPLZ
Q
50%
tPZH
tPHZ
1.3 V
Q
Figure 3.
tf
VCC
GND
tPLH
tTLH
VCC
GND
HIGH
IMPEDANCE
10%
VOL
90%
VOH
HIGH
IMPEDANCE
LATCH
ENABLE
50%
tw
tPLH
tPHL
Q
50%
Figure 2.
INPUT D
LATCH
ENABLE
VALID
50%
tsu
th
50%
Figure 4.
VCC
GND
VCC
GND
VCC
GND
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
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