CS61880-IQ Ver la hoja de datos (PDF) - Cirrus Logic
Número de pieza
componentes Descripción
Lista de partido
CS61880-IQ Datasheet PDF : 70 Pages
| |||
CS61880
SYMBOL
WR/DS/SDI
RD/RW
ALE/AS/SCLK
CS/JASEL
LQFP
84
85
86
87
FBGA
J14
J13
J12
J11
TYPE
I
I
I
I
DESCRIPTION
Write Enable/Data Strobe/Serial Data
Intel Parallel Host Mode - This pin, “WR”, functions as
a write enable.
Motorola Parallel Host Mode - This pin, “DS“, functions as
a data strobe input.
Serial Host Mode - This pin, “SDI”, functions as the serial
data input.
Hardware Mode - This pin is not used and should be con-
nected to ground.
Read Enable/Read/Write
Intel Parallel Host Mode - This pin, “RD”, functions as a
read enable.
Motorola Parallel Host Mode - This pin, “R/W”, functions
as the read/write input signal.
Hardware Mode - This pin is not used and should be con-
nected to ground.
Address Latch Enable/Address Strobe/Serial Clock
Intel Parallel Host Mode - This pin, “ALE”, functions as the
Address Latch Enable when configured for multiplexed ad-
dress/data operation.
Motorola Parallel Host Mode - This pin, “AS”, functions as
the active “low” address strobe when configured for multi-
plexed address/data operation.
Serial Host Mode - This pin, “SCLK”, is the serial clock
used for data I/O on SDI and SDO.
Hardware Mode - This pin is not used and should be con-
nected to ground.
Chip Select Input/Jitter Attenuator Select
Host Mode - This active low input is used to enable ac-
cesses to the microprocessor interface in either serial or
parallel mode.
Hardware Mode - This pin controls the position of the Jitter
Attenuator.
Table 3. Jitter Attenuation Selection
Pin State
LOW
HIGH
OPEN
Jitter Attenuation Position
Transmit Path
Receive Path
Disabled
12
DS450PP2
Share Link: 