CS61880-IQ Ver la hoja de datos (PDF) - Cirrus Logic

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CS61880-IQ

Octal E1 Line Interface Unit

Cirrus Logic 

CS61880

SYMBOL

RCLK7

RPOS7/RDATA7

RNEG7/BPV7

LQFP

143

142

141

FBGA

A1

A2

A3

TYPE

O

O

O

DESCRIPTION

Receive Clock Output Port 7

Receive Positive Pulse/ Receive Data Output Port 7

Receive Negative Pulse/Bipolar Violation Output Port 7

3.7 Analog RX/TX Data I/O

SYMBOL

TTIP0

TRING0

RTIP0

RRING0

TTIP1

TRING1

RTIP1

RRING1

TTIP2

LQFP

45

46

48

49

52

51

55

54

57

FBGA

N5

P5

P7

N7

L5

M5

M7

L7

L10

TYPE

O

O

I

I

O

O

I

I

O

DESCRIPTION

Transmit Tip Output Port 0

Transmit Ring Output Port 0

These pins are the differential outputs of the transmit driver.

The driver internally matches impedances for E1 75 Ω or

E1 120 Ω lines requiring only a 1:1.15 transformer. The

CBLSEL pin is used to select the appropriate line matching

impedance only in “Hardware” mode. In host mode, the ap-

propriate line matching impedance is selected by the Line

Length Data Register (11h) (See Section 14.18 on

page 38).

NOTE: TTIP and TRING are forced to a high impedance state

when the TCLK or the TXOE pin is forced “Low”.

Receive Tip Input Port 0

Receive Ring Input Port 0

These pins are the differential line inputs to the receiver.

The receiver uses either Internal Line Impedance or Exter-

nal Line Impedance modes to match the line impedances

for E1 75Ω or E1 120Ω modes.

Internal Line Impedance Mode - The receiver uses the

same external resistors to match the line impedance (Refer

to Figure 16 on page 50).

External Line Impedance Mode - The receiver uses differ-

ent external resistors to match the line impedance (Refer to

Figure 17 on page 51).

- In host mode, the appropriate line impedance is selected

by the Line Length Data Register (11h) (See Section

14.18 on page 38).

- In hardware mode, the CBLSEL pin selects the appropri-

ate line impedance. (Refer to Table 4 on page 15 for proper

line impedance settings).

NOTE: Data and clock recovered from the signal input on

these pins are output via RCLK, RPOS, and RNEG.

Transmit Tip Output Port 1

Transmit Ring Output Port 1

Receive Tip Input Port 1

Receive Ring Input Port 1

Transmit Tip Output Port 2

DS450PP2

19

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