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NM95MS16

Plug and Play Front-End Devices for ISA-BUS Systems

Fairchild Semiconductor 

Connection Diagrams (Continued)

Signals

SA<11:0>

IORD*

IOWR*

AEN

SD<7:0>

OSC (Note 1)

RSTDRV

CS

Type

I

I

I

I

I/O

I

I

I

SK, DI

I

DO

O

IRQOUT<5:0>

O

IRQIN<1:0>

I

DRQin/SA<15>

I

DACKOUT* /IOCS2*

O

ISADRQ<1:0>/IRQOUT<7:6>

O

ISADACK<1:0>*/SA<13:12>

I

IOCS<1:0>*

O

IRQIN<1>/SA<14>

I

Description

Address inputs from the ISA bus.

I/O read strobe from the ISA bus.

I/O write strobe from the ISA bus.

Address Enable from ISA Bus —used in conjunction with DMA.

Data bus —lower byte —from/to the ISA bus.

“OSC” clock from the ISA bus —used for internal state machines.

Reset input from the ISA bus.

Chip select for Microwire port. There should be a pull down

resistor of 4.7k on CS pin if unused externally, or directly

connected to GND.

Clock and Data input lines for Microwire bus connection to access

a portion (4k) on chip EEPROM.

Data output line for the Microwire interface detailed above.

Connection to ISA bus interrupt request pins. On-chip interrupt

request(s) may be connected to any 6 of the ISA IRQ lines.

Interrupt request from on-board logic

DMA request from on-board logic, or Address input from ISA bus

depending on mode selected.

DMA Acknowledge for on-board logic or Programmable chipselect

(2) depending on mode selected.

Connection for two ISA bus DMA Request lines, or additional

interrupt request lines depending on the mode selected.

DMA Acknowledge from the ISA bus or additional address lines

depending on the mode selected.

Programmable chip selects to address on-board peripheral.

Interrupt request from on board logic or Address input from ISA bus

depending on mode selected.

*Signal name with a “*” means its an active low signal.

Note 1: “OSC” clock from ISA Bus is fixed at a standard frequency of 14.318 MHz. NM95MS16 is designed and tested for 14.318 MHz. However NM95MS16 can handle

frequencies up to 24 MHz though it is not 100% tested.

3

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