SM8213 Ver la hoja de datos (PDF) - Nippon Precision Circuits
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SM8213 Datasheet PDF : 33 Pages
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SM8213AM
Battery Saving (BS1, BS2, BS3)
The SM8213AM controls the intermittent-duty oper-
ation of the RF stage, which reduces battery con-
sumption, and three output control signals (BS1,
BS2, BS3). The function each signal controls in each
mode is described below.
s BS1 (RF-control main output signal)—The RF
stage is active when BS1 is HIGH. The rising-
edge setup time for receive timing is set by flags
RF0 to RF5 (61 steps). The maximum setup time
is 25.417 ms at 2400 bps, 50.833 ms at 1200 bps,
and 119.141 ms at 512 bps. Note that 3EH and
3FH are invalid settings for BS1.
s BS2 (RF DC-level adjustment signal)—BS2 is
used to control the discharge of the receive signal
DC-cut capacitor. The function of BS2 is deter-
mined by flag BS2, as described below.
• When flag BS2 is 0, pin BS2 goes HIGH
together with BS1 and then goes LOW again
after the BS1 setup time (idle mode). In pream-
ble and lock mode (during address/message
reception), it stays LOW.
• When flag BS2 is 1, pin BS2 goes HIGH during
lock mode sync code receive timing and idle
mode signal receive timing. In preamble mode,
it stays LOW.
s BS3 (PLL setup signal)—BS3 is used to control
PLL operation when the PLL is used. The rising-
edge setup time for receive timing is set by flags
PL0 to PL5 (61 steps). The maximum setup time
is 25.833 ms at 2400 bps, 51.667 ms at 1200 bps,
and 121.094 ms at 512 bps. Note that 3FH is an
invalid setting for BS3.
Note that the setup times should be set up such that
(BS3 rising-edge setup time) > (BS1 rising-edge
setup time).
Receive code
BS1
BS2
(flag BS2 option = 0)
BS2
(flag BS2 option = 1)
BS3
Receive code
01234567
Address does not match
01234567
Self address
1.953*Nms (0.833*Nms)
[0.417*Nms]
1.953*Nms (0.833*Nms)
[0.417*Nms]
1.953*Mms
(0.833*Mms) [0.417*Mms]
1.953*Mms
(0.833*Mms) [0.417*Mms]
01234567
01234567
BS1
BS2
(flag BS2 option = 0)
BS2
(flag BS2 option = 1)
BS3
BREAK command
Self address
BREAK detection to reception stop (32 bit max.)
Figure 3. BS1, BS2 and BS3 timing (Lock mode, frame 3)
NIPPON PRECISION CIRCUITS—10
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