MC100E101FN(2003) Ver la hoja de datos (PDF) - ON Semiconductor

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MC100E101FN
(Rev.:2003)

5V ECL Quad 4-Input OR/NOR Gate

ON Semiconductor 

MC10E101, MC100E101

Q

Driver

Device

Q

50 W

50 W

D

Receiver

Device

D

V TT

VTT = VCC − 2.0 V

Figure 1. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020 − Termination of ECL Logic Devices.)

Resource Reference of Application Notes

AN1404

− ECLinPS Circuit Performance at Non−Standard VIH Levels

AN1405

− ECL Clock Distribution Techniques

AN1406

− Designing with PECL (ECL at +5.0 V)

AN1503

− ECLinPS I/O SPICE Modeling Kit

AN1504

− Metastability and the ECLinPS Family

AN1568

− Interfacing Between LVDS and ECL

AN1596

− ECLinPS Lite Translator ELT Family SPICE I/O Model Kit

AN1650

− Using Wire−OR Ties in ECLinPS Designs

AN1672

− The ECL Translator Guide

AND8001

− Odd Number Counters Design

AND8002

− Marking and Date Codes

AND8020

− Termination of ECL Logic Devices

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