HS-80C86RH Ver la hoja de datos (PDF) - Intersil

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HS-80C86RH

Radiation Hardened 16-Bit CMOS Microprocessor

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Waveforms (Continued)

CLK (HS-82C85RH OUTPUT)

TCHCTV

M/IO

TCLAV

BHE/S7, A19/S6-A16/S3

TCLLH

ALE

RDY (HS-82C85RH INPUT)

SEE NOTE 49

READY (HS-80C86RH INPUT)

HS-80C86RH

T1

T2

T3

T4

TCLCL

TCH1CH2

TCL2CL1

TW

TCHCL

TCLCH

TCLDV

TCLAX

BHE, A19-A16

TLHLL

TLLAX

S7-S3

TCHLL

VIH

TAVLL

VIL

TR1VCL

TCLRIX

TRYLCL

TCHRYX

TCHCTV

TCLAV

AD15-AD0

READ CYCLE

(NOTE 46)

(WR, INTA = VOH)

RD

DT/R

TCHCTV

DEN

TCLAZ

AD15-AD0

TAZRL

TCLRL

TCVCTV

TRYHCH

TDVCL

TCLDX1

DATA IN

TCLRH

TRHAV

TRLRH

TCVCTX

TCHCTV

NOTES:

FIGURE 2. BUS TIMING - MINIMUM MODE SYSTEM

46. All signals switch between VOH and VOL unless otherwise specified.

47. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.

48. Two INTA cycles run back-to-back. The HS-80C86RH local ADDR/DATA bus is inactive during both INTA cycles. Control signals are shown for

the second INTA cycle.

49. Signals at HS-82C85RH are shown for reference only.

50. All timing measurements are made at 1.5V unless otherwise noted.

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