HS-82C55ARH Ver la hoja de datos (PDF) - Intersil

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HS-82C55ARH

Radiation Hardened CMOS Programmable Peripheral Interface

Intersil 

Waveforms

RD

INPUT

CS, A1, A0

TPVRL

TAVRL

HS-82C55ARH

TRLRH

TRHPX

TRHAX

WR

D7 - D0

CS, A1, A0

TAVWL

TWLWH

TDVWH

TWHDX

TWHAX

D7 - D0

TRLDV

TRHDZ

FIGURE 1. MODE 0 (BASIC INPUT)

STB

TSLSH

IBF

TSLIH

INTR

TSHNH

TRLNL

TRHIL

RD

INPUT FROM

PERIPHERAL

TPVSH

TSHPX

FIGURE 3. MODE 1 (STROBED INPUT)

WR

OBF

TWHOL

INTR

ACK

STB

DATA FROM CPU

TO HS-82C55ARH

TKLOH

TSLSH

TKLKH

IBF

PERIPHERAL

BUS

TSLIH

TKLPV

TPVSH

TSHPX

RD

DATA FROM PERI-

PHERAL TO

HS-82C55ARH

DATA FROM

HS-82C55ARH

TO PERIPHERAL

TKHPX

TRHIL

DATA FROM

HS-82C55ARH

TO CPU

FIGURE 5. MODE 2 (BIDIRECTIONAL)

NOTE: Any sequence where WR occurs before ACK and STB

occurs before RD is permissible.

4

OUTPUT

TWHPV

FIGURE 2. MODE 0 (BASIC OUTPUT)

WR

OBF

TWHOL

TKLOH

INTR

TWLNL

ACK

OUTPUT

TWHPV

TKLKH

TKHNH

FIGURE 4. MODE 1 (STROBED OUTPUT)

A0 - A1, CS

DATA BUS

WR

TAVWL

TWHAX

TDVWH

TWLWH

FIGURE 6. WRITE TIMING

TWHDX

A0 - A1, CS

RD

DATA BUS

TAVRL

TAVRL

HIGH IMPEDANCE

TRLRH

TRHAX

TRHDX

VALID HIGH IMPEDANCE

FIGURE 7. READ TIMING

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