HB52R1289E22-B6B Ver la hoja de datos (PDF) - Elpida Memory, Inc

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HB52R1289E22-B6B

1 GB Registered SDRAM DIMM 128-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 64 M × 4 Components) PC100 SDRAM

Elpida Memory, Inc 

HB52R1289E22-A6B/B6B

AC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (cont)

HB52R1289E22

-A6B/B6B

Parameter

PC100

Symbol Symbol Min

Max

Unit Notes

CKE hold time

t CEH

Command setup time

t CS

Command hold time

t CH

Ref/Active to Ref/Active command period tRC

Active to precharge command period

t RAS

Active command to column command tRCD

(same bank)

Thi

3.0

Tsi

2.6

Thi

3.0

Trc

70

Tras

50

Trcd

20

—

ns

1

—

ns

1

—

ns

1

—

ns

1

120000 ns

1

—

ns

1

Precharge to active command period

t RP

Trp

20

—

ns

1

Write recovery or data-in to precharge tDPL

Tdpl

20

—

ns

1

lead time

Active (a) to Active (b) command period tRRD

Trrd

20

—

ns

1

Transition time (rise to fall)

tT

1

5

ns

Refresh period

t REF

—

64

ms

Notes: 1. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.5 V.

2. Access time is measured at 1.5 V. Load condition is CL = 50 pF.

3. tLZ (min) defines the time at which the outputs achieves the low impedance state.

4. tHZ (max) defines the time at which the outputs achieves the high impedance state.

5. tCES defines CKE setup time to CK rising edge except power down exit command.

Test Conditions

• Input and output timing reference levels: 1.5 V

• Input waveform and output load: See following figures

• Ambient illuminance: Under 100 lx

input

2.4 V

2.0 V

0.4 V 0.8 V

tT

tT

DQ

CL

Data Sheet E0017H20

13

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