HB52RF1289E2-75B Ver la hoja de datos (PDF) - Elpida Memory, Inc

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HB52RF1289E2-75B

1 GB Registered SDRAM DIMM 128-Mword × 72-bit, 133 MHz Memory Bus, 2-Bank Module (36 pcs of 64 M × 4 Components) PC133 SDRAM

Elpida Memory, Inc 

HB52RF1289E2-75B

DC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)

HB52RF1289E2-75B

Parameter

Symbol Min

Max

Unit Test conditions Notes

Operating current

I CC1

—

Standby current in power ICC2P

—

down

3215

803

Burst length = 1 1, 2, 3

mA

tRC = min

mA

CKE = VIL, tCK = 12 6

ns

Standby current in power ICC2PS

—

down (input signal stable)

767

mA

CKE = VIL, tCK = ∞ 7

Standby current in non ICC2N

—

power down

Active standby current in ICC3P

—

power down

1415

839

mA

CKE, S = VIH,

4

tCK = 12 ns

mA

CKE = VIL, tCK = 12 1, 2, 6

ns

Active standby current in ICC3N

—

non power down

Burst operating current

I CC4

—

Refresh current

I CC5

—

Self refresh current

I CC6

—

Input leakage current

I LI

–10

Output leakage current ILO

–10

1775

3575

5195

803

10

10

mA

CKE, S = VIH,

tCK = 12 ns

1, 2, 4

tCK = min, BL = 4 1, 2, 5

mA

tRC = min

3

mA

mA

VIH ≥ VCC – 0.2 V

8

VIL ≤ 0.2 V

µA

0 ≤ Vin ≤ VCC

µA

0 ≤ Vout ≤ VCC

DQ = disable

Output high voltage

VOH

2.4

—

V

IOH = –4 mA

Output low voltage

VOL

—

0.4

V

IOL = 4 mA

Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the

output open condition.

2. One bank operation.

3. Input signals are changed once per one clock.

4. Input signals are changed once per two clocks.

5. Input signals are changed once per four clocks.

6. After power down mode, CK operating current.

7. After power down mode, no CK operating current.

8. After self refresh mode set, self refresh current.

Data Sheet E0018H10

10

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