V54C3128404V Ver la hoja de datos (PDF) - Mosel Vitelic Corporation

Número de pieza

componentes Descripción

Lista de partido

V54C3128404V

128Mbit SDRAM 3.3 VOLT, BGA PACKAGE 8M X 16 16M X 8 32M X 4

Mosel Vitelic Corporation  

MOSEL VITELIC

Timing Diagrams

1. Bank Activate Command Cycle

2. Burst Read Operation

3. Read Interrupted by a Read

4. Read to Write Interval

4.1 Read to Write Interval

4.2 Minimum Read to Write Interval

4.3 Non-Minimum Read to Write Interval

5. Burst Write Operation

6. Write and Read Interrupt

6.1 Write Interrupted by a Write

6.2 Write Interrupted by Read

7. Burst Write & Read with Auto-Precharge

7.1 Burst Write with Auto-Precharge

7.2 Burst Read with Auto-Precharge

8. Burst Termination

8.1 Termination of a Burst Write Operation

8.2 Termination of a Burst Write Operation

9. AC- Parameters

9.1 AC Parameters for a Write Timing

9.2 AC Parameters for a Read Timing

10. Mode Register Set

11. Power on Sequence and Auto Refresh (CBR)

12. Power Down Mode

13. Self Refresh (Entry and Exit)

14. Auto Refresh (CBR)

V54C3128(16/80/40)4V(BGA)

V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001

15

Share Link: