CS5460-BS Ver la hoja de datos (PDF) - Cirrus Logic
Número de pieza
componentes Descripción
Lista de partido
CS5460-BS Datasheet PDF : 34 Pages
| |||
CS5460
10 kΩ
5 kΩ
L1 N
L2
500 Ω
500 Ω
10 Ω
470 nF
100 µF
0.1 µF
14
VA+
3
VD+
0.1 µF
R1
R2
To Service
RPI *
RS
0.1 µF
9 VIN+
CPV*
CS5460
PFMON 17
CPUCLK 2
XOUT 1
10 VIN-
16 IIN+
XIN 24
CP *
I
15 IIN-
12 VREFIN
11 VREFOUT
RESET 19
CS 7
SDI 23
SDO 6
SCLK 5
INT 20
EDIR 22
EOUT 21
VA- DGND
13
4
2.5 MHz to
20 MHz
Optional
Clock
Source
Serial
Data
Interface
* Refer to Input Current Protection
Figure 4. Typical Connection Diagram (One-Phase 3-Wire)
2.2 Performing Measurements
The CS5460 performs measurements of instanta-
neous current, instantaneous voltage, instantaneous
power, energy, RMS current, and RMS voltage.
These measurements are output as 24-bit signed
and unsigned data formats as a percentage of full
scale. The flow of data to perform these calcula-
tions is shown in Figure 5. All of these measure-
ments begin when a start conversion command is
given. The energy and RMS registers are then up-
dated every N conversions (or 1 computation cy-
cle) where N is the content of the Cycle Count
register. After the computation cycle has finished,
the DRDY bit in the Status and Mask register is set.
The INT pin will also become active if the DRDY
bit is unmasked.
Table 1 provides an example detailing the output
linearity. A computation cycle is derived from the
master clock and its frequency is
(MCLK/K)/(1024*N). Instantaneous calculations
are performed at a 4000 Hz rate where as, IRMS,
VRMS, and energy, are performed at a 1 Hz rate. Al-
so, DRDY is set only after computation cycles are
complete (i.e. there is no indicator flag to indicate
when the instantaneous conversions are read; how-
ever, if the Cycle Count register were set to 1, all
output calculations would be instantaneous and
DRDY would indicate when instantaneous calcula-
tions were finished).
Range
Max Input
Linearity
(After
Calibration)
Output word
Energy
Vrms
Irms
1000:1
2:1
500:1
See Analog Characteristics
0.1% of
reading
0.1% of
reading
0.1% of
reading
24-bits
Table 1. Specification with MCLK = 4.096 MHz, K = 1,
and N = 4000.
10
DS279PP5
Share Link: 