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CL-PS7500FE-QC-A

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

TABLE OF CONTENTS

CONVENTIONS.....................................................................................................................12

1. PIN INFORMATION ...............................................................................................................13

1.1 Pin Diagram......................................................................................................................................13

1.2 Block Diagram ..................................................................................................................................14

2. PIN DESCRIPTIONS .............................................................................................................15

2.1 CL-PS7500FE Pin Descriptions .......................................................................................................15

2.2 Power and Ground Pins....................................................................................................................22

2.3 Numerical Pin Listing........................................................................................................................24

3. FUNCTIONAL DESCRIPTION..............................................................................................27

3.1 Functional Block Diagram.................................................................................................................27

3.2 ARM Processor Macrocell ................................................................................................................27

3.3 FPA Macrocell...................................................................................................................................27

3.4 Video and Sound Macrocell..............................................................................................................29

3.5 Clock Control and Power Management ............................................................................................29

3.6 Memory System ...............................................................................................................................29

3.6.1 DMA..................................................................................................................................30

3.6.2 I/O Control ........................................................................................................................30

3.7 Other Features .................................................................................................................................31

3.8 Test Modes .......................................................................................................................................31

3.9 Structure of the CL-PS7500FE.........................................................................................................31

3.9.1 Register Programming......................................................................................................32

3.9.2 Interaction Between Macrocells........................................................................................32

3.10 Resetting CL-PS7500FE Systems ...................................................................................................32

4. THE ARM PROCESSOR MACROCELL ..............................................................................33

4.1 Architecture ......................................................................................................................................33

4.2 Instruction Set ..................................................................................................................................33

4.3 Memory Interface..............................................................................................................................34

4.4 Clocks and Synchronous/Asynchronous Modes ..............................................................................34

5. IDC .........................................................................................................................................35

5.1 Cacheable Bit ...................................................................................................................................35

5.2 IDC Operation...................................................................................................................................35

5.2.1 IDC Validity .......................................................................................................................35

5.2.2 Software IDC Flush...........................................................................................................35

5.2.3 Doubly-Mapped Space .....................................................................................................35

5.2.4 Read-Locked-Write...........................................................................................................36

5.3 IDC Enable/Disable and Reset .........................................................................................................36

5.3.1 Enable the IDC .................................................................................................................36

5.3.2 Disable the IDC.................................................................................................................36

5.4 Write Buffer (WB) .............................................................................................................................36

5.4.1 Bufferable Bit ....................................................................................................................36

5.4.2 Write Buffer Operation ......................................................................................................36

5.4.3 Enable the Write Buffer.....................................................................................................37

5.4.4 Disable the Write Buffer ....................................................................................................37

5.5 Coprocessors ...................................................................................................................................37

June 1997

ADVANCE DATA BOOK v2.0

3

TABLE OF CONTENTS

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