CL-PS7500FE-QC-A Ver la hoja de datos (PDF) - Cirrus Logic
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CL-PS7500FE-QC-A Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
7.7 Register 2: Level One Page Table (Write only) .................................................................................64
7.8 Register 3: Domain Access Control (Write only) ..............................................................................64
7.9 Register 4: Reserved ........................................................................................................................64
7.10 Register 5: Fault Status/Translation Lookaside Buffer Flush ............................................................65
7.11 Register 6: Fault Address/TLB Purge ...............................................................................................65
7.12 Register 7: IDC Flush (Write only) ....................................................................................................65
7.13 Registers 8–15: Reserved ................................................................................................................65
8. MEMORY MAP ......................................................................................................................66
9. MEMORY SUBSYSTEMS .....................................................................................................67
9.1 ROM Interface ..................................................................................................................................67
9.1.1 ROM Bank Configuration and Timing ...............................................................................68
9.2 DRAM Interface ................................................................................................................................69
9.2.1 DRAM Control Registers ..................................................................................................69
9.2.2 DRAM Address Multiplexing ............................................................................................70
9.2.3 Selection Between 16- and 32-bit DRAM .........................................................................70
9.2.4 EDO and Timing Mode Selection .....................................................................................71
9.2.5 DRAM Refresh..................................................................................................................72
9.2.6 DRAM Self-Refresh ..........................................................................................................73
9.2.7 Non-Sequential Access Time and RAS Precharge ..........................................................73
9.3 DMA Channels .................................................................................................................................74
9.3.1 Video DMA.......................................................................................................................74
9.3.2 Cursor DMA .....................................................................................................................75
9.3.3 Sound DMA .....................................................................................................................75
9.3.4 The Sound DMA State Machine .......................................................................................76
10. MEMORY AND I/O PROGRAMMERS’ MODEL...................................................................78
10.1 Introduction.......................................................................................................................................78
10.2 Register Summary............................................................................................................................78
10.3 Register Descriptions .......................................................................................................................81
10.3.1 IOCR (0x00) — I/O Control...............................................................................................81
10.3.2 KBDDAT (0x04) — Keyboard Data ...................................................................................81
10.3.3 KBDCR (0x08) — Keyboard Control.................................................................................82
10.3.4 IOLINES (0x0C) — IOP[7:0] Port Control.........................................................................83
10.3.5 IRQSTA (0x10) — IRQ A Interrupts Status.......................................................................83
10.3.6 IRQRQA (0x14) — IRQ A Interrupts Request/Clear.........................................................84
10.3.7 IRQMSKA (0x18) — IRQ A Interrupts Mask.....................................................................84
10.3.8 SUSMODE (0x1C) — SUSPEND Mode...........................................................................85
10.3.9 IRQSTB (0x20) — IRQ B Interrupts Status ......................................................................85
10.3.10 IRQRQB (0x24) — IRQ B Interrupts Request ..................................................................86
10.3.11 IRQMSKB (0x28) — IRQ B Interrupts Mask.....................................................................86
10.3.12 STOPMODE (0x2C) — STOP Mode ................................................................................87
10.3.13 FIQST (0x30) — FIQ Interrupts Status .............................................................................87
10.3.14 FIQRQ (0x34) — FIQ Interrupts Request .........................................................................87
10.3.15 FIQMSK (0x38) — FIQ Interrupts Mask ...........................................................................88
10.3.16 CLKCTL (0x3C) — Clock Control .....................................................................................88
10.3.17 T0low (0x40) — Timer 0 Low Bits.....................................................................................89
10.3.18 T0high (0x44) — Timer 0 High Bits...................................................................................89
10.3.19 T0GO (0x48) — Timer 0 Go Command............................................................................89
10.3.20 T0LAT (0x4C) — Timer 0 Latch Command.......................................................................89
June 1997
ADVANCE DATA BOOK v2.0
5
TABLE OF CONTENTS
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