LT1683 Ver la hoja de datos (PDF) - Linear Technology
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LT1683 Datasheet PDF : 26 Pages
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LT1683
APPLICATIONS INFORMATION
So if we wanted to turn on at 20V with 2V of hysteresis:
RA
=
2V
•
1.39V − 20V •
24µA • 1.39V
0.1V
=
23.4k
RB
=
2V • 1.39V − 20V • 0.1V
24µA •(20V − 1.39V)
= 1.75k
Resistor values could be altered further by adding Zeners
in the divider string. A resistor in series with SHDN pin
could further change hysteresis without changing turn-on
voltage.
Frequency Compensation
Loop frequency compensation is accomplished by way of
a series RC network on the output of the error amplifier
(VC pin).
RVC
2k
CVC
0.01µF
VC PIN
CVC2
4.7nF
1683 F06
Figure 6
Referring to Figure 6, the main pole is formed by capaci-
tor CVC and the output impedance of the error amplifier
(approximately 400kΩ). The series resistor, RVC, creates a
“zero” which improves loop stability and transient response.
A second capacitor, CVC2, typically one-tenth the size of
the main compensation capacitor, is sometimes used to
reduce the switching frequency ripple on the VC pin. VC
pin ripple is caused by output voltage ripple attenuated
by the output divider and multiplied by the error amplifier.
Without the second capacitor, VC pin ripple is:
VCPINRIPPLE
=
1.25
•
VRIPPLE •
VOUT
gm
• R VC
where VRIPPLE = Output ripple (VP-P )
gm = Error amplifier transconductance
RVC = Series resistor on VC pin
VOUT = DC output voltage
To prevent irregular switching, VC pin ripple should be
kept below 50mVP-P . Worst-case VC pin ripple occurs at
16
maximum output load current and will also be increased
if poor quality (high ESR) output capacitors are used. The
addition of a 0.0047µF capacitor for CVC2 pin reduces
switching frequency ripple to only a few millivolts. A low
value for RVC will also reduce VC pin ripple, but loop phase
margin may be inadequate.
Setting Current Limit
The sense resistor sets the value for maximum operating
current. When the CS pin voltage is 0.1V the gate drivers will
immediately go low (no slew control). Therefore the sense
resistor value should be set to RS = 0.1V/ISW(PEAK), where
ISW(PEAK) is the peak current in the MOSFETs. ISW(PEAK)
will depend on the topology and component values and
tolerances. Certainly it should be set below the saturation
current value for the transformer.
If CS pin voltage is 0.22V in addition to the drivers going
low, VC and SS will be discharged to ground. This is to
provide additional protection in the event of a short cir-
cuit. By discharging VC and SS, the MOSFET will not be
stressed as hard on subsequent cycles since the current
trip will be set lower.
Turn-off of the MOSFETs will normally be inhibited for
about 100ns at the start of every turn on cycle. This is
to prevent noise from interfering with normal operation
of the controller. This current sense blanking does not
prevent the outputs from be turned off in the event of
a fault. Slewing of the gate voltage effectively provides
additional blanking.
Traces to the SENSE resistor should be kept short and
wide to minimize resistance and inductance. Large
interwinding capacitance in the transformer or high
capacitance on the drain of the MOSFETs will produce
a current pulse through the sense resistor during drain
voltage slewing. The magnitude of the pulse is C • dV/dt
where C is the capacitance and dV/dt is the voltage slew
rate which is controlled by the part. This pulse will increase
the sensed current on switch turn-on and can cause pre-
mature MOSFET turn-off. If this occurs, the transformer
may need a different winding technique (see AN39) or
alternatively, a blanking circuit can be used. Please contact
the LTC applications group for support if required.
1683fd
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