80930HD Ver la hoja de datos (PDF) - Intel
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80930HD Datasheet PDF : 38 Pages
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8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 10. Signal Description (Sheet 2 of 4)
Signal
Name
EA#
ECAP
ECI
INT1:0#
OVRI#
P0.7:0
P1.0
P1.1
P1.2
P1.5:3
P1.6
P1.7
P2.7:0
P3.0
P3.1
P3.3:2
P3.5:4
P3.6
P3.7
PLLSEL2:0
PSEN#
RD#
Type
Description
I External Access. Directs program memory accesses to on-
chip or off-chip code memory. When EA# is connected to
ground, all program memory accesses are off-chip. When EA#
is connected to VCC, program accesses on-chip ROM if the
address is within the range of the on-chip ROM; otherwise, the
access is off-chip. The value of EA# is latched at reset. For
devices without on-chip ROM, EA# must be connected to
ground.
I External Capacitor. Connect a 1 µF or larger capacitor
between this pin and VSS to ensure proper operation of the
differential line drivers.
I PCA External Clock Input. External clock input to the 16-bit
PCA timer.
I External Interrupts 0 and 1. These inputs set the IE1:0
interrupt flags in the TCON register. Bits IT1:0 in TCON select
the triggering method: edge-triggered (high-to-low) or level
triggered (active low). INT1:0 also serves as external run
control for timer1:0 when selected by GATE1:0# in TCON.
I Overcurrent Sense. Senses input to indicate an overcurrent
condition for a bus-powered USB device on an external
downstream port. Active low.
I/O Port 0. This is an 8-bit, open-drain, bidirectional I/O port.
I/O Port 1. This is an 8-bit, bidirectional I/O port with internal pull-
ups.
I/O Port 2. An 8-bit, bidirectional I/O port with internal pull-ups.
I/O Port 3. An 8-bit, bidirectional I/O port with internal pull-ups.
I Phase-locked Loop Select. Three-bit code selects USB data
rate (see Table 13 on page 17).
O Program Store Enable. Read signal output. Asserted for the
memory address range determined by bits RD1:0 in configu-
ration byte UCONFIG0 (see RD# and Table 11).
O Read. Read signal output to external data memory. Asserted
only for RD1:0 = 11. See configuration byte UCONFIG0. (Also
see PSEN# and Table 11).
Alternate
Function
—
—
P1.2
P3.3:2
—
AD7:0
T2
T2EX
ECI
CEX2:0
CEX3/WAIT#
CEX4/A17/WCLK
A15:8
RXD
TXD
INT1:0#
T1:0
WR#
RD#/A16
—
—
P3.7/A16
ADVANCE INFORMATION
13
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