80930HD Ver la hoja de datos (PDF) - Intel
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80930HD Datasheet PDF : 38 Pages
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8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
5.0 ADDRESS MAP
Table 12. 8x930Hx Address Map
Internal
Address)
Description
Notes
FF:FFFFH
FF:4000H
External Memory except the top eight bytes (FF:FFF8H – FF:FFFFH) which are
reserved for the configuration array.
1, 2, 3
FF:FFFFH External memory or on-chip nonvolatile memory (8 Kbytes FF:0000H –
FF:0000H FF:1FFFH, 16 Kbytes FF:0000H – FF:3FFFH).
2, 4, 5
FE:FFFFH
FE:0000H
External Memory
2
FD:FFFFH
02:0000H
Reserved Addresses
6
01:FFFFH
01:0000H
External Memory
2
00:FFFFH
00:0420H
External Memory
4
00:041FH
00:0080H
On-chip RAM
4
00:007FH
00:0020H
On-chip RAM
7
00:001FH
00:0000H
Storage for R0–R7 of Register File
8, 9
NOTES:
1. 18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).
2. Data in this area is accessible by indirect addressing only.
3. Eight addresses at the top of all external memory maps are reserved for current and future device
Configuration Byte information.
4. Data is accessible by direct and indirect addressing.
5. Devices reset into internal or external starting locations depending on the state of EA# and configura-
tion byte information. See EA# signal description in Table 5. See also UCONFIG1:0 bit definitions in
the 8x930Ax, 8x930Hx Universal Serial Bus Micorcontroller User’s Manual.
6. This reserved area returns unspecified values. Software can execute a write to the reserved area, but
nothing is actually written.
7. Data is accessible by direct, indirect, and bit addressing.
8. The special function registers (SFRs) and the register file have separate internal address spaces.
9. Data is accessible by direct, indirect, and register addressing.
16
ADVANCE INFORMATION
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