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BT864AKPF

YCrCb to NTSC/PAL Digital Video Encoder

Conexant Systems 

Bt864A/865A

YCrCb to NTSC/PAL Digital Video Encoder

1.0 Circuit Description

1.2 Clock Timing

1.2 Clock Timing

A clock signal with a frequency twice the pixel sampling rate must be present at

the CLK pin. The device generates an internal pixel CLOCK that in slave mode is

synchronized to the HSYNC* pin. This signal is used to increment the horizontal

pixel and vertical line counters and to register the pixel (P[7:0], Y[7:0], TTXDAT,

RESET*, BLANK*, SLAVE, HSYNC*, and VSYNC*) inputs. All setup and

hold timing specifications are measured with respect to the rising edge of CLK.

1.3 Pixel Input Timing

1.3.1 8-bit YCrCb Input Mode

The 8-bit YCrCb multiplexed input mode is selected by default. Multiplexed Y,

Cb, and Cr data is input through the P[7:0] inputs. By default, the input sequence

for active video pixels must be Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3, etc. in

accordance with CCIR656.

1.3.2 16-bit YCrCb Input Mode

The 16-bit mode is selected by setting the YC16 register bit. Y data is input

through the Y[7:0] inputs. Multiplexed Cb and Cr data is input through the P[7:0]

inputs.

1.3.3 Pixel Synchronization

The default input pixel sequence is such that the next clock after HSYNC* goes

low will be the start of the 4-byte Cb/Y/Cr/Y sequence in 8-bit mode, or Y/Cb

sample pair in 16-bit mode. This is true for slave mode, and for master mode with

the default HSYNC* timing. This sequence can be changed by the SYNCDLY

and CBSWAP bits in both master and slave modes, or by using the variable

HSYNC* timing in master mode.

The SYNCDLY bit will decrease the delay between the HSYNC* pin and the

analog output by one clock cycle. The pixel-to-analog out timing is unaffected.

This makes the next pixel after the falling edge of HSYNC* the last Y of the

Cb/Y/Cr/Y sequence in 8-bit mode.

The CBSWAP bit will shift the sequence at the input such that the next sample

after the falling edge of HSYNC* will be the Cr sample of the Cb/Y/Cr/Y

sequence in 8-bit mode, or the Y/Cr sample pair in 16-bit mode. The relationship

between the HSYNC* pin and the analog output is unaffected, as is the

pixel-to-analog out timing.

100138B

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