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BT864AKPF

YCrCb to NTSC/PAL Digital Video Encoder

Conexant Systems 

Bt864A/865A

YCrCb to NTSC/PAL Digital Video Encoder

Figure 1-3. HSYNC* Timing In Master Mode

Internal Pixel

Clock/Counter

Internal

Horizontal Reset

HSYNC*

Reset

(4) 1 2 3 . . .

Pixel Count

Default

(3)

(2)

(1)

1.0 Circuit Description

1.4 HSYNC* Timing

(4) 1 2 3 . . .

Pixel Count

Default

(2)

(1)

Analog Output

Video Waveform

Horizontal Sync

Pipeline Delay

Active

Video

Color

Burst

NOTE(S):

(1) One clock delay (1/2 pixel) of HSYNC* falling edge, using register SYNCDLY.

(2) Falling edge of HSYNC* is definable in variable HSYNC* timing mode, using the register HSYNCF.

(3) Rising edge of HSYNC* is definable in variable HSYNC* timing mode, using the register HSYNCR.

(4) Maximum horizontal resolution (see Table 1-2).

5. Waveforms not to scale.

1.4.2 Slave Mode

Slave mode does not support a variable HSYNC* timing mode. The default

pipeline delay from the HSYNC* falling edge to analog sync out falling edge is

47 clocks if SYNCDLY = 0, and 46 clocks if SYNCDLY = 1. The default delay

from the falling edge of HSYNC* input to internal horizontal pixel counter reset

is 5 clocks. In both master and slave modes, the pixel data pipeline delay is 52

clocks.

100138B

Conexant

1-7

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