RTL8196E
Datasheet
7. Memory Controller
The RTL8196E integrates a memory control module to access external DDR DRAM , SDR DRAM, and
Flash memory.
The interface is designed for DDR-compliant DDR DRAM, and designed for PC133 or PC166-compliant
SDR DRAM, and supports auto-refresh mode, which requires a 4096 refresh cycle within 64ms. The
DRAM interface supports one chip (MCS0#), and the DRAM size and timing is configurable in registers.
The RTL8196E supports one flash memory chip (SF_CS0#). The interface supports SPI flash memory.
When Flash is used, the system will boot from KSEG1 at virtual address 0xBFC0_0000 (physical
address: 0x1FC0_0000).
7.1. SDR DRAM Control Interface
PC100~PC166-compliant SDR DRAM is supported. The SDR DRAM controller supports Auto Refresh
mode, which requires a 4096-cycle refresh each 64ms. The RTL8196E provides a maximum of 512Mbit
address space (8Mx16x4Banks) and the SDR DRAM size is configurable.
7.1.1. Features
• Interface (Bus Width): 16-bit
• Targeted SDR Frequency: Up to 168MHz
• Supports one Chip Select (MCS0#)
• Supported SDR DRAM Chip Specification:
Bank Counts: 2, 4
Row Counts: 2K (A0~A10), 4K (A0~A11), 8K (A0~A12)
Column Counts: 256 (A0~A7), 512 (A0~A8), 1K (A0~A9), 2K (A0~A9, A11)
• Programmable Timing Parameters: tRAS, tRP, tRCD, tCL, tREFI…
5-Port 10/100M Ethernet Router Network Processor
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Track ID: JATR-3375-16 Rev. 1.0