FS6159-01 Ver la hoja de datos (PDF) - AMI Semiconductor
Número de pieza
componentes Descripción
Lista de partido
FS6159-01 Datasheet PDF : 15 Pages
| |||
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer IC
Table 3: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN
TYPE
NAME
DESCRIPTION
SUPPLY
2
DI
4
DI
36, 37
DO
42, 43, 46,
47, 50, 51
DO
6, 7, 10, 11, 14,
15, 17, 18,
DO
21, 22, 24, 25
33
DI
54, 55
DO
30
DI
29
DIO
27, 28, 34
DI
40
P
38
P
44, 45, 52
P
3
P
8, 12, 16,
20, 26
P
56
P
32
P
39
P
35
P
41, 48, 49
P
1
P
5, 9, 13,
19, 23
P
53
P
31
P
14REF
66REF
CK48_0:1
One 14.318MHz clock input, used to develop the REF and CK48 clock outputs
One 66.67MHz clock input, used to develop the CK66 and PCI clock outputs
Two 48MHz clock outputs
CK66_0:5 Six 66MHz clock outputs, developed as buffered copies of the 66REF reference input
PCI_0:11
Twelve 33.33MHz PCI clock outputs, developed as a divide-by-two of the 66REF reference
input. Groups of PCI outputs can be disabled via SEL_Q, SEL_R, and SEL_S (see Table 4).
Individual outputs can be disabled via the serial interface.
PWR_DWN#
Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all
clocks in low state.
REF_0:1 Two 3.3V REF clock outputs, developed as buffered copies of the 14REF reference input
SCL
SMBus serial interface clock input
SDA
SMBus serial interface data input/output
SEL_Q
SEL_R
SEL_S
Three clock management select inputs, used to enable, disable, or tristate groups of clock
outputs
VDD
3.3V ± 5% power supply for PLL core
VDD_48 3.3V power supply for CK48 clock outputs
VDD_66 3.3V power supply for CK66 clock outputs
VDD_N 3.3V power supply for the 14REF and the 66REF reference inputs
VDD_P 3.3V power supply for the PCI clock outputs
VDD_R
VDD_S
VSS
VSS_48
VSS_66
VSS_N
3.3V power supply for the REF clock outputs
3.3V power supply for the serial interface and digital input pins
Ground for the PLL core
Ground for the CK48 clock outputs
Ground for the CK66 clock outputs
Ground for the 14REF and the 66REF reference inputs
VSS_P Ground for the PCI clock outputs
VSS_R
VSS_S
Ground for REF clock outputs
Ground for the serial interface and digital input pins
VDD_N
VDD_N
VDD_48
VDD_66
VDD_P
VDD_S
VDD_R
VDD_S
VDD_S
VDD_S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ISO9001
2.27.02
2
Share Link: 