FS6158-01 Ver la hoja de datos (PDF) - AMI Semiconductor
Número de pieza
componentes Descripción
Lista de partido
FS6158-01 Datasheet PDF : 14 Pages
| |||
FS6158-01
Two-Way/Four Way Motherboard Clock Generator/Buffer IC
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN
47
21
22
23
2
14
27
17, 18
45, 44
42, 41
39, 38
36, 35
33, 32
30, 29
8
9
24
16
11
19
13
28, 34, 40, 46
25
7
3, 48
12
15
20
31, 37, 43
26
10
1, 6
4
5
ISO9001
TYPE
DI
DIO
DIO
DIO
DO
DO
AI
DI
AO
AO
AO
AO
AO
AO
DO
DO
DI
DI
P
P
P
P
P
P
P
P
P
P
P
P
P
AI
AO
NAME
APICON
APIC_0
SEL_A
APIC_1
SEL_B
APIC_2
SS_EN#
14REF
66REF
IREF
ISEL_0
ISEL_1
HOST_P1
HOST_N1
HOST_P2
HOST_N2
HOST_P3
HOST_N3
HOST_P4
HOST_N4
HOST_P5
HOST_N5
HOST_P6
HOST_N6
MREF_P
MREF_N
PWR_DWN#
SEL133/100#
VDD
VDD_A
VDD_66
VDD_H
VDD_I
VDD_M
VDD_R
VSS
VSS_66
VSS_A
VSS_H
VSS_I
VSS_M
VSS_R
XIN
XOUT
DESCRIPTION
Enables (logic-high) or disables (logic-low) the optional 1.8V APIC clocks
One of three optional APIC clocks, enabled or disabled by APICON
One of two frequency select inputs, used in combination with SEL133/100#. Input signal levels
are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high.
One of three optional APIC clocks, enabled or disabled by APICON
One of two frequency select inputs, used in combination with SEL133/100#. Input signal levels
are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high.
One of three optional APIC clocks, enabled or disabled by APICON
Active-low spread spectrum enable turns on spread spectrum modulation of PLL clocks. Input
levels are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high.
One 14.318MHz clock output, provided as a reference clock to the companion clock device
One 66.67MHz clock output, provided as a reference clock to the companion clock device
A fixed precision resistor from this pin to ground provides a reference current used for the
differential current-mode HOST clock outputs
The logic setting on these two pins selects the multiplying factor of the IREF reference current
for the HOST pair outputs
Host clock pair #1; one of six pairs of current-steering differential current-mode outputs. The
current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1
Host clock pair #2; one of six pairs of current-steering differential current-mode outputs
Host clock pair #3; one of six pairs of current-steering differential current-mode outputs
Host clock pair #4; one of six pairs of current-steering differential current-mode outputs
Host clock pair #5; one of six pairs of current-steering differential current-mode outputs
Host clock pair #6; one of six pairs of current-steering differential current-mode outputs
One clock in a pair of outputs provided as a reference clock to a memory clock driver
One clock (180° out of phase with MREF_P) in a pair of outputs provided as a reference clock
to a memory clock driver
Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all
clocks in low state. Complete clock cycles on all outputs will occur before shut down begins.
Selects 133MHz or 100MHz Host clock frequency
3.3V core power supply
1.8V power supply for optional APIC clocks or a 3.3V supply to pins 21-23
3.3V power supply for 66REF clock output
3.3V power supply for the differential HOST clock outputs
3.3V power supply for IREF current reference input
3.3V power supply for MREF clock outputs
3.3V power supply for the 14REF clock output and the crystal oscillator
Core Ground
Ground for the 66REF clock output
Ground for the APIC clock outputs
Ground for the differential HOST clock outputs
Ground for IREF current reference input
Ground for the MREF clock outputs
Ground for the 14REF clock output and the crystal oscillator
14.318MHz crystal oscillator input
14.318MHz crystal oscillator output
2
SUPPLY
VDD_R
VDD_A
VDD_A,
VDD_H
VDD_A
VDD_A,
VDD_H
VDD_A
VDD_A,
VDD_H
VDD_R
VDD_66
VDD_I
VDD_66
VDD_H
VDD_H
VDD_H
VDD_H
VDD_H
VDD_H
VDD_M
VDD_M
VDD_I
VDD_66
-
-
-
-
-
-
-
-
-
-
-
-
-
VDD_R
VDD_R
2.26.02
Share Link: 