DM9102AE Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.
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DM9102AE Datasheet PDF : 71 Pages
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DM9102A
Single Chip Fast Ethernet NIC Controller
5. Pin Description
I = Input, O = Output, I/O = Input / Output, O/D = Open Drain, P = Power,
LI = reset Latch Input, # = asserted Low
5.1 PCI Bus Interface Signals
Pin No.
128QFP/128LQFP
113
Pin Name
INT#
114
RST#
115
PCICLK
117
GNT#
118
REQ#
119
PME#
3
IDSEL
21
FRAME#
23
IRDY#
24
TRDY#
26
DEVSEL#
I/O
Description
O/D Interrupt Request
This signal will be asserted low when an interrupt condition
as defined in CR5 is set, and the corresponding mask bit in
CR7 is cleared
I System Reset
When this signal is low, the DM9102A performs the internal
system reset to its initial state
I PCI System Clock
PCI bus clock that provides timing for DM9102A related to
PCI bus transactions. The clock frequency range is up to
40MHz
I Bus Grant
This signal is asserted low to indicate that DM9102A has
been granted ownership of the bus by the central arbiter
O Bus Request
The DM9102A will assert this signal low to request the
ownership of the bus
O/D Power Management Event.
Open drain. Active Low. The DM9102A drive it low to
indicates that a power management event has occurred
I Initialization Device Select
This signal is asserted high during the Configuration Space
read/write access
I/O Cycle Frame
This signal is driven low by the DM9102A master mode to
indicate the beginning and duration of a bus transaction
I/O Initiator Ready
This signal is driven low when the master is ready to
complete the current data phase of the transaction. A data
phase is completed on any clock when both IRDY# and
TRDY# are sampled asserted
I/O Target Ready
This signal is driven low when the target is ready to complete
the current data phase of the transaction. During a read, it
indicates that valid data is asserted. During a write, it
indicates the target is prepared to accept data
I/O Device Select
The DM9102A asserts the signal low when it recognizes its
target address after FRAME# is asserted. As a bus master,
the DM9102A will sample this signal that insures its
Final
7
Version: DM9102A-DS-F07
April 12, 2002
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