DM9102F Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.
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DM9102F Datasheet PDF : 63 Pages
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Network Interface
Pin No.
107
108
112
113
Clock Pins
Pin No.
118
119
120
121
Miscellaneous Pins
Pin No.
91
102
104
105
122
Pin Name
RXI-
RX+
TXO-
TXO+
Pin Name
OSCVDD
X1/OSC
X2
OSCGND
Pin Name
SELROM
NC
BGRES
BGGND
PWRIN
DM9102
10/100Mbps Single Chip LAN Controller
I/O
Description
I
100M/10Mbps Differential Input Pair.
These two pins are differential receive input pair for
100BASE-TX and 10BASE-T. They are capable of
receiving 100BASE-TX MLT-3 or 10BASE-T
Manchester encoded data.
O
100M/10Mbps Differential Output Pair.
These two pins are differential output pair for
100BASE-TX and 10BASE-T. This output pair
provides controlled rise and fall times designed to
filter the transmitter output.
I/O
Description
P Analog Power
I Crystal or Oscillator Input. (25MHZŘ 50ppm)
O Crystal feedback output pin used for crystal
connection only. Leave this pin open if oscillator is
used.
P Analog Ground
I/O
Description
LI Multiplex mode/Direct mode Selection.
This pin is “reset latch input at power up” to select
Multiplex mode or direct mode.
“0” = multiplex mode (default),
“1” = direct mode. At direct mode, this is also a output
pin which is used by MA6.
O No Connection
I Band-gap Voltage Reference Resistor.
It connects to a 6200 , 1% error tolerance resistor
between this pin and BGGND pin (pin 105) to provide
an accurate current reference for DM9102.
I Ground for Band-gap circuit
I VDD clamp
This pin is used to identify the D3(cold) power state in
a power management aware system. This pin should
be connected to the PCI power, while other DVDD
pins should be connected to the auxiliary power, if
any. In non-power management aware systems, or
there is no auxiliary power, the DVDD pins and the
PWRIN pins should be connected to the PCI power
10
Final
Version: DM9102-DS-F03
August 30, 2000
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