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DM9008 Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.

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DM9008
Davicom
Davicom Semiconductor, Inc. Davicom
DM9008 Datasheet PDF : 68 Pages
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Transmit Configuration Register (TCR)
DM9008
ISA/Plug & Play Super Ethernet Contoller
The transmit configuration register determines the actions of the transmitter section of the DM9008 during transmission of a packet on
the network. LB1 and LB0 power up as 0.
7
6
5
4
3
2
1
0
--
--
--
OFST
ATD
LB1
LB0
CRC
Bit
Symbol
Description
D0
CRC
Inhibit CRC
0: CRC appended by transmitter
1: CRC inhibited by transmitter
D1
LB0
Encoded Loopback Control: These encoded configuration bits set the type of loopback that
D2
LB1
is to be performed. Note that loopback in mode 2 sets the ENA in loopback mode and
that D3 of the DCR must be set to zero for loopback operation
LB1
Mode 0 0
Mode 1 0
Mode 2 1
Mode 3 1
LB0
0
Normal Operation
1
ENC module Loopback
0
ENA module Loopback
1
Loopback to Coax
D3
ATD
Auto Transmit Disable: This bit allows another station to disable the DM9008 transmitter by
transmission of a particular multicast packet. The transmitter can be re-enabled by
resetting this bit or by reception of a second particular multicast packet
0: Normal Operation
1: Reception of multicast address hashing to bit 62 disables transmitter; reception of
multicast address hashing to bit 63 enables transmitter
D4
OFST
Collision Offset Enable: This bit modifies the backoff algorithm to allow propitiation of
nodes
0: Backoff Logic implements normal algorithm
1: Forces Backoff algorithm modification to 0 to 2 min(3+n,10) slot times for first
three collisions, then follows standard backoff. (For first three collisions, station has
higher average backoff delay, resulting in a low priority mode.)
D5
--
Reserve must be set to zero
D6
--
Reserved
D7
--
Reserved
Final
17
Version: DM9008-DS-F02
November 30, 2000

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