GL640USB Ver la hoja de datos (PDF) - Genesys Logic

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GL640USB

IEEE-1284 to USB Bridge

Genesys Logic 

6. Block Diagram

GL640USB, GL640USB-A

GL640USB

Micro Controller

I/O

Register

USB Control

Register

ENDP0

FIFO

EPP

Engine

FIFO0

(64 bytes)

FIFO1

(64 bytes)

USB

SIE

This USB controller contains 3 sets of FIFO. The ENDP0 FIFO is an 8-byte FIFO to store/transmit the

endp0 control packet. The FIFO0 and FIFO1 are a set of 64-byte ping-pong FIFO for endp1 and endp2. FIFO0

is used for DATA0 packet and FIFO1 is for DATA1 packet. When they are served as the endp1 FIFO, the

LINKFF bit of FFCFG should be set and LINKDIR bit of FFCFG should be cleared. It they are allocated as the

endp1 FIFO, then LINKDIR should be set.

An EPP engine is included to automatically accessing data to/from external device ASIC. Firmware can set

the data length and hardware will count down to decide the last byte.

There are two sets of registers : I/O register and USB register. The USB register is controlled by

micro-controller to implement the USB endpoint 0 functions. The I/O register is the main register to interface the

data accessing between this controller and external device.

Revision 1.1

-7-

Jun. 7, 1999

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