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LPC47N227TQFP

100 Pin Super I/O with LPC Interface for Notebook Applications

SMSC -> Microchip 

3.3 Volt Operation / 5 Volt Tolerance

The LPC47N227 is a 3.3 Volt part. It is intended

solely for 3.3V applications. Non-LPC bus pins

are 5V tolerant; that is, the input voltage is 5.5V

max, and the I/O buffer output pads are

backdrive protected.

The LPC interface pins are 3.3 V only. These

signals meet PCI DC specifications for 3.3V

signaling. These pins are:

• LAD[3:0]

• nLFRAME

• nLDRQ

• nLPCPD

The input voltage for all other pins is 5.5V max.

These pins include all non-LPC Bus pins and the

following pins:

• nPCI_RESET

• PCI_CLK

• SER_IRQ

• nCLKRUN

• nIO_PME

connected to VCC. The VTR pin generates a VTR

Power-on-Reset signal to initialize these

components.

Note: If VTR is to be used for programmable

wake-up events when VCC is removed, VTR must

be at its full minimum potential at least 10 µs

before VCC begins a power-on cycle. When VTR

and VCC are fully powered, the potential

difference between the two supplies must not

exceed 500mV.

Internal PWRGOOD

An internal PWRGOOD logical control is included

to minimize the effects of pin-state uncertainty in

the host interface as VCC cycles on and off.

When the internal PWRGOOD signal is “1”

(active), VCC > 2.3V (nominal), and the

LPC47N227 host interface is active. When the

internal PWRGOOD signal is “0” (inactive), VCC ≤

2.3V (nominal), and the LPC47N227 host

interface is inactive; that is, LPC bus reads and

writes will not be decoded.

Power Functionality

The LPC47N227 has two power planes: VCC

and VTR.

VCC Power

The LPC47N227 device pins nIO_PME, nRI1,

nRI2, and most GPIOs (as input) are part of the

PME interface and remain active when the

internal PWRGOOD signal has gone inactive,

provided VTR is powered. See Trickle Power

Functionality section.

The LPC47N227 is a 3.3 Volt part. The VCC

Trickle Power Functionality

supply is 3.3 Volts (nominal). See the

Operational Description Section and the

Maximum Current Values subsection.

When the LPC47N227 is running under VTR

only, the PME wakeup events are active and (if

enabled) able to assert the nIO_PME pin active

VTR Support

low. The following lists the wakeup events:

• UART 1 Ring Indicator

The LPC47N227 requires a trickle supply (VTR) to

provide sleep current for the programmable

• UART 2 Ring Indicator

• GPIOs for wakeup. See below.

wake-up events in the PME interface when VCC is

removed. The VTR supply is 3.3 Volts (nominal).

See the Operational Description Section. The

maximum VTR current that is required depends

on the functions that are used in the part. See

Trickle Power Functionality subsection and the

Maximum Current Values subsection. If the

LPC47N227 is not intended to provide wake-up

capabilities on standby current, VTR can be

The following requirements apply to all I/O pins

that are specified to be 5 volt tolerant.

ƒ I/O buffers that are wake-up event

compatible are powered by VCC. Under

VTR power (VCC=0), these pins may only

be configured as inputs. These pins have

input buffers into the wakeup logic that are

powered by VTR.

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