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LPC47N227TQFP

100 Pin Super I/O with LPC Interface for Notebook Applications

SMSC -> Microchip 

FUNCTIONAL DESCRIPTION

Super I/O Registers

Host Processor Interface (LPC)

The address map, shown below in Table 1,

shows the addresses of the different blocks of

the Super I/O immediately after power up. The

base addresses of the FDC, serial and parallel

ports, runtime register block and configuration

register block can be moved via the configuration

registers. Some addresses are used to access

more than one register.

The host processor communicates with the

LPC47N227 through a series of read/write

registers via the LPC interface. The port

addresses for these registers are shown in Table

1. Register access is accomplished through I/O

cycles or DMA transfers. All registers are 8 bits

wide.

Table 1 - Super I/O Block Addresses

ADDRESS

BLOCK NAME

NOTES

Base+(0-5) and +(7)

Floppy Disk

Base+(0-7)

Serial Port Com 1

Base1+(0-7)

Serial Port Com 2 IR Support

Base2+(0-7)

FIR and CIR

Parallel Port

Base+(0-3)

SPP

Base+(0-7)

EPP

Base+(0-3), +(400-402)

ECP

Base+(0-7), +(400-402)

ECP+EPP+SPP

Base + (0-F)

Runtime Registers

Base + (0-1)

Configuration

Note 1: Refer to the configuration register descriptions for setting the base address.

16

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