LPC47N227TQFP Ver la hoja de datos (PDF) - SMSC -> Microchip
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LPC47N227TQFP Datasheet PDF : 202 Pages
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Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins.
DT1 DT0
0
0
1
0
0
1
1
1
Table 9 – DRVDEN Mapping0
DRVDEN1 (1)
DRVDEN0 (1)
DRIVE TYPE
DRATE0
DENSEL
4/2/1 MB 3.5"
2/1 MB 5.25" FDDS
2/1.6/1 MB 3.5" (3-MODE)
DRATE0
DRATE1
DRATE0
nDENSEL PS/2
DRATE1
DRATE0
Table 10 – Default Precompensation Delays
PRECOMPENSATIO
DATA RATE
N DELAYS
2 Mbps
20.8 ns
1 Mbps
41.67 ns
500 Kbps
125 ns
300 Kbps
125 ns
250 Kbps
125 ns
Main Status Register (MSR)
Address 3F4 READ ONLY
The Main Status Register is a read-only register and indicates the status of the disk controller. The Main
Status Register can be read at any time. The MSR indicates when the disk controller is ready to receive
data via the Data Register. It should be read before each byte transferring to or from the data register
except in DMA mode. No delay is required when reading the MSR after a data transfer.
7
6
5
4
3
2
1
0
NON
CMD
DRV1 DRV0
RQM
DIO
DMA BUSY Reserved Reserved BUSY BUSY
BIT 0 - 1 DRV x BUSY
These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped
seeks and recalibrates.
BIT 4 COMMAND BUSY
This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has
been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek,
Recalibrate commands), this bit is returned to a 0 after the last command byte.
BIT 5 NON-DMA
This mode is selected in the SPECIFY command and will be set to a 1 during the execution phase of a
command. This is for polled data transfers and helps differentiate between the data transfer phase and the
reading of result bytes.
BIT 6 DIO
Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write
is required.
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