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LPC47N227-MN

100 Pin Super I/O with LPC Interface for Notebook Applications

SMSC -> Microchip 

ƒ LPC Bus Host Interface

- Multiplexed Command, Address and

Data Bus

- 8-Bit I/O Transfers

- 8-Bit DMA Transfers

- 16-Bit Address Qualification

- Serial IRQ Interface Compatible with

Serialized IRQ Support for PCI

Systems

- PCI nCLKRUN Support

- Power Management Event (nIO_PME)

Interface Pin

ƒ 100 Pin TQFP Package and STQFP

Package

GENERAL DESCRIPTION

The SMSC LPC47N227 is a 3.3V PC 99 and

ACPI 1.0b compliant Super I/O Controller. The

LPC47N227 implements the LPC interface, a pin

reduced ISA interface which provides the same

or better performance as the ISA/X-bus with a

substantial savings in pins used. The part also

includes 29 GPIO pins.

The LPC47N227 incorporates SMSC’s true

CMOS 765B floppy disk controller, advanced

digital data separator, 16-byte data FIFO, two

16C550 compatible UARTs, one Multi-Mode

parallel port with ChiProtect circuitry plus EPP

and ECP support and one floppy direct drive

support. The LPC47N227 does not require any

external filter components, is easy to use and

offers lower system cost and reduced board

area. The LPC47N227 is software and register

compatible with SMSC’s proprietary 82077AA

core.

The true CMOS 765B core provides 100%

compatibility with IBM PC/XT and PC/AT

architectures and provides data overflow and

underflow protection. The SMSC advanced

digital data separator incorporates SMSC’s

patented data separator technology allowing for

ease of testing and use. The LPC47N227

supports both 1Mbps and 2Mbps data rates and

vertical recording operation at 1Mbps Data Rate.

The LPC47N227 also features a full 16-bit

internally decoded address bus, a Serial IRQ

interface with PCI nCLKRUN support, relocatable

configuration ports and three DMA channel

options.

Both on-chip UARTs are compatible with the

NS16C550. One UART includes additional

support for a Serial Infrared Interface that

complies with IrDA v1.2 (Fast IR), HPSIR, and

ASKIR formats (used by Sharp and other PDAs),

as well as Consumer IR.

The parallel port is compatible with IBM PC/AT

architectures, as well as IEEE 1284 EPP and

ECP. The parallel port ChiProtect circuitry

prevents damage caused by an attached

powered printer when the LPC47N227 is not

powered.

The LPC47N227 incorporates sophisticated

power control circuitry (PCC). The PCC supports

multiple low power down modes. The

LPC47N227 also features Software Configurable

Logic (SCL) for ease of use. SCL allows

programmable system configuration of key

functions such as the FDC, parallel port, and

UARTs.

The LPC47N227 supports the ISA Plug-and-Play

Standard (Version 1.0a) and provides the

recommended functionaity to support Windows

‘95/’98 and PC99. The I/O Address, DMA

Channel and Hardware IRQ of each device in the

LPC47N227 may be reprogrammed through the

internal configuration registers. There are 192

I/O address location options, a Serialized IRQ

interface, and three DMA channels.

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