FDC87W21 Ver la hoja de datos (PDF) - SMSC -> Microchip
Número de pieza
componentes Descripción
Lista de partido
FDC87W21 Datasheet PDF : 164 Pages
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PIN DESCRIPTION
(Note: Refer to the DC Characteristics Section for details.)
I/O8tc
I/O12t
I/O24t
OUT8t
OUT12t
OD12
OD24
INt
INts
INc
INcs
TTL level output pin with 8 mA source-sink capability; CMOS level input voltage
TTL level bi-directional pin with 12 mA source-sink capability
TTL level bi-directional pin with 24 mA source-sink capability
TTL level output pin with 8 mA source-sink capability
TTL level output pin with 12 mA source-sink capability
Open-drain output pin with 12 mA sink capability
Open-drain output pin with 24 mA sink capability
TTL level input pin
TTL level Schmitt-triggered input pin
CMOS level input pin
CMOS level Schmitt-triggered input pin
Host Interface
SYMBOL PIN
D0−D7
A0−A9
A10
IOCHRDY
66-73
51-55
57-61
75
5
MR
6
nCS
2
nDACK_N
IRSL1
IRSL2
AEN
62
nIOR
63
nIOW
64
DRQ_B
100
nDACK_B
98
DRQ_C
4
nDACK_C
18
TC
97
IRQIN
93
DRQ_D
IRSL2
IRRXH/
IRSL0
IRQ_A
96
GIO1
IRQ_B
92
GIO0
IRQ_C
44
I/O
I/O24t
INt
INt
OD24
INts
INt
INt
OUT12t
OUT12t
INt
INts
INts
OUT12t
INts
OUT12t
INts
INts
INt
OUT12t
OUT12t
I/O12t
OUT12t
I/O12t
OUT12t
I/O12t
OUT12t
FUNCTION
HOST INTERFACE
System data bus bits 0-7
System address bus bits 0-9
In ECP Mode, this pin is the A10 address input.
In EPP Mode, this pin is the IO Channel Ready output to extend the
host read/write cycle.
Master Reset. Active high. MR is low during normal operations.
Active low chip select signal.
DMA acknowledge signal D.
IR module mode select 1.
IR module mode select 2.
System address bus enable
CPU I/O read signal
CPU I/O write signal
DMA request signal B
DMA Acknowledge signal B
DMA request signal C
DMA Acknowledge signal C
Terminal Count. When active, this pin indicates termination of a
DMA transfer.
Interrupt request input.
DMA request signal D.
IR module mode selection 2.
When input, act as a function of high speed IR receiving terminal.
When output selected, act as a IR module mode selection 0.
When CR16 Bit 4 (GOIQSEL) = 0: Interrupt request signal A;
When CR16 Bit 4 (GOIQSEL) = 1: General Purpose I/O port 1.
When CR16 Bit 4 (GOIQSEL) = 0: Interrupt request signal B;
When CR16 Bit 4 (GOIQSEL) = 1: General Purpose I/O port 0.
Interrupt request signal C
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