LPC61W492 Ver la hoja de datos (PDF) - SMSC -> Microchip

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LPC61W492

Integrated Super I/O Controller for LPC Bus with Game and MIDI Ports/Plus Hardware Monitoring Functions

SMSC -> Microchip 

CRF3 (Default 0x00)

Bit 7 - 6: Reserved. Return zero when read.

Bit 5 - 0: Device's IRQ status.

These bits indicate the IRQ status of the individual device respectively. The device's IRQ status bit

is set by their source device and is cleared by writing a 1. Writing a 0 has no effect.

Bit 5: MOUIRQSTS. MOUSE IRQ status.

Bit 4: KBCIRQSTS. KBC IRQ status.

Bit 3: PRTIRQSTS. printer port IRQ status.

Bit 2: FDCIRQSTS. FDC IRQ status.

Bit 1: URAIRQSTS. UART A IRQ status.

Bit 0: URBIRQSTS. UART B IRQ status.

CRF4 (Default 0x00)

Bit 7 - 6: Reserved. Return zero when read.

Bit 5 - 0: These bits indicate the IRQ status of the individual GPIO function or logical device

respectively. The status bit is set by their source function or device and is cleared by writing a 1.

Writing a 0 has no effect.

Bit 5: HMIRQSTS. Hardware monitor IRQ status.

Bit 4: WDTIRQSTS. Watch dog timer IRQ status.

Bit 3: CIRIRQSTS. Consumer IR IRQ status.

Bit 2: MIDIIRQSTS. MIDI IRQ status.

Bit 1: IRQIN1STS. IRQIN1 status.

Bit 0: IRQIN0STS. IRQIN0 status.

CRF6 (Default 0x00)

Bit 7 - 6: Reserved. Return zero when read.

Bit 5 - 0: Enable bits of the nSMI/nPME generation due to the device's IRQ.

These bits enable the generation of an nSMI/nPME interrupt due to any IRQ of the devices.

nSMI/nPME logic output = (MOUIRQEN and MOUIRQSTS) or (KBCIRQEN and KBCIRQSTS) or

(PRTIRQEN and PRTIRQSTS) or (FDCIRQEN and FDCIRQSTS) or

(URAIRQEN and URAIRQSTS) or (URBIRQEN and URBIRQSTS) or

(HMIRQEN and HMIRQSTS) or (WDTIRQEN and WDTIRQSTS) or

(IRQIN3EN and IRQIN3STS) or (IRQIN2EN and IRQIN2STS) or

(IRQIN1EN and IRQIN1STS) or (IRQIN0EN and IRQIN0STS)

Bit 5: MOUIRQEN.

= 0 Disable the generation of an nSMI/nPME interrupt due to MOUSE's IRQ.

= 1 Enable the generation of an nSMI/nPME interrupt due to MOUSE's IRQ.

Bit 4: KBCIRQEN.

= 0 Disable the generation of an nSMI/nPME interrupt due to KBC's IRQ.

= 1 Enable the generation of an nSMI/nPME interrupt due to KBC's IRQ.

Bit 3: PRTIRQEN.

= 0 Disable the generation of an nSMI/nPME interrupt due to printer port's IRQ.

= 1 Enable the generation of an nSMI/nPME interrupt due to printer port's IRQ.

Bit 2: FDCIRQEN.

= 0 Disable the generation of an nSMI/nPME interrupt due to FDC's IRQ.

= 1 Enable the generation of an nSMI/nPME interrupt due to FDC's IRQ.

Bit 1: URAIRQEN.

= 0 Disable the generation of an nSMI/nPME interrupt due to UART A's IRQ.

= 1 Enable the generation of an nSMI/nPME interrupt due to UART A's IRQ.

Bit 0: URBIRQEN.

= 0 Disable the generation of an nSMI/nPME interrupt due to UART B's IRQ.

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