LPC61W492 Ver la hoja de datos (PDF) - SMSC -> Microchip

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LPC61W492

Integrated Super I/O Controller for LPC Bus with Game and MIDI Ports/Plus Hardware Monitoring Functions

SMSC -> Microchip 

Logical Device B (Hardware Monitor)

CR30 (Default 0x00)

Bit 7 - 1: Reserved.

Bit 0: = 1 Activates the logical device.

= 0 Logical device is inactive.

CR60, CR 61 (Default 0x00, 0x00)

These two registers select Hardware Monitor base address [0x100:0xFFF] on 8-byte boundary.

CR70 (Default 0x00)

Bit 7 - 4: Reserved.

Bit 3 - 0: These bits select IRQ resource for Hardware Monitor.

CRF0 (Default 0x00)

Bit 7 - 1: Reserved.

Bit 0: Disable initial abnormal beep (VcoreA and +3.3 V)

= 0 Enable power-on abnormal beep

= 1 Disable power-on abnormal beep

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