LAN83C171 Ver la hoja de datos (PDF) - SMSC -> Microchip
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LAN83C171
SMSC -> Microchip
LAN83C171 Datasheet PDF : 90 Pages
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FUNCTIONAL DESCRIPTION
The LAN83C171 EPIC/100 is a high
performance Ethernet network controller
designed to interface directly to the PCI Local
Bus on one side and to the 802.3 standard
Media Independent Interface (MII) on the other
side. The network interface can also be
configured to communicate directly with the
LAN83C694 10BASE-T transceiver.
The LAN83C171 implements 802.3 Media
Access Control functions. It is capable of
running at Ethernet rates of both 100 Mb/s and
10 Mb/s. An
MII compliant serial
management interface is provided to control
external media dependent transceivers. The
LAN83C171 is a two channel bus master (one
for transmit, one for receive) capable of
transferring data at the maximum PCI transfer
rate of 132 Mbps. Buffer format in host memory
is controlled by an independent linked list
structure for each channel.
The LAN83C171's architecture is essentially
broken into two independent transmit and
receive processes which share PCI bus and
network bandwidth. This architecture is ideal for
full-duplex networks where transmission and
reception of frames may occur simultaneously.
An internal arbiter controls which process has
access to the PCI bus at a given time (see
section on "transmit/receive arbitration for PCI
bus").
The transmit process consists of a DMA
controller, local transmit RAM, memory transfer
unit ("MTU") and CSMA/CD transmit state
machine. The transmit DMA copies packet data
from host memory into the local buffer. When
ready, the memory transfer unit feeds data from
the transmit buffer to the CSMA/CD state
machine, which is responsible for sending data
out on the network under the Ethernet protocol.
When transmission is complete, the transmit
DMA posts the transmit status into host
memory, interrupts the host (optionally) and
looks for the next transmit packet to be queued.
Like the transmit process, the receive process
consists of a DMA controller, local receive RAM,
memory transfer unit and CSMA/CD state
machine. Packets are received by the
CSMA/CD state machine and stored into local
memory by the receive MTU. The receive DMA
then copies the data from the local buffer into
host memory, posts the receive status and
interrupts the host. The LAN83C171 has several
features designed to minimize CPU utilization,
including the optional Receive Lookahead
Buffering Mode, which eliminates the need to re-
copy the data from one host memory location to
another. Figure 1 on the following page shows
a block diagram of the LAN83C171.
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